Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control FET)
Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback terminal (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.(1)
Do not allow switching current to flow under the device.
DRVH and DRVL line should not run close to SW node or minimize it. (2)
GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected to SGND. (3)
GND terminals for capacitors of VREG5 and VIN should be connected to PGND. (4)
Signal lines should not run under/near Output Inductor or minimize it. (5)
11.2 Layout Example
Reference designators shown correspond to the schematic of Figure 28.