ZHCSL89B may 2020 – november 2020 TPS3703
PRODUCTION DATA
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and the SENSE pin voltage is within a valid window ((VIT-(UV) < VSENSE < VIT+(OV)), RESET is deasserted after the reset delay time (tD). If MR is not controlled externally, then MR can either be connected to VDD or left floating because the MR pin is internally pulled up to VDD. Figure 8-2 shows the relation between MR and RESET.