ZHCSDQ6C April   2015  – March 2024 TPS3702-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input (SENSE)
      2. 6.3.2 Outputs (UV, OV)
      3. 6.3.3 User-Configurable Accuracy Band (SET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > UVLO)
      2. 6.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 6.4.3 Power-On Reset (VDD < V(POR))
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Window Voltage Detector Considerations
      2. 7.1.2 Input and Output Configurations
      3. 7.1.3 Immunity to SENSE Pin Voltage Transients
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

GUID-53ED5223-038D-4BAE-B1C8-229E155A69A6-low.gif Figure 4-1 DDC Package
SOT-6
Top View
Table 4-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1UVOActive-low, open-drain undervoltage output. This pin goes low when the SENSE voltage falls below the internally set undervoltage threshold (VIT–). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.
2GND—Ground
3SENSEIInput for the monitored supply voltage rail. When the SENSE voltage goes below the undervoltage threshold, the UV pin is driven low.
When the SENSE voltage goes above the overvoltage threshold, the OV pin is driven low.
4SETIUse this pin to configure the threshold voltages.
Refer to Table 8-1 for the desired configuration.
5VDDISupply voltage input pin. To power the device, connect a voltage supply (within the range of 2V and 18V) to VDD.
Good analog design practice is to place a 0.1μF ceramic capacitor close to this pin.
6OVOActive-low, open-drain overvoltage output. This pin goes low when the SENSE voltage rises above the internally set overvoltage threshold (VIT+). See the timing diagram in Figure 5-1 for more details. Connect this pin to a pull-up resistor terminated to the desired pull-up voltage.