ZHCSO90A november   2022  – april 2023 TPS36-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 器件比较
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Supervisor
      2. 8.3.2 Window Watchdog Timer
        1. 8.3.2.1 tWC (Close Window) Timer
        2. 8.3.2.2 tWO (Open Window) Timer
        3. 8.3.2.3 Watchdog Enable Disable Operation
        4. 8.3.2.4 tSD Watchdog Start Up Delay
        5. 8.3.2.5 SET Pin Behavior
      3. 8.3.3 Manual RESET
      4. 8.3.4 RESET and WDO Output
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 CRST Delay
        1. 9.1.1.1 Factory-Programmed Reset Delay Timing
        2. 9.1.1.2 Adjustable Capacitor Timing
      2. 9.1.2 Watchdog Window Functionality
        1. 9.1.2.1 Factory-Programmed watchdog Timing
        2. 9.1.2.2 Adjustable Capacitor Timing
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1: Monitoring Microcontroller Supply and Watchdog During Operational and Sleep Modes
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Setting Voltage Threshold
          2. 9.2.1.2.2 Determining Window Timings During Operation and Sleep Modes
          3. 9.2.1.2.3 Meeting the Minimum Reset Delay
          4. 9.2.1.2.4 Setting the Watchdog Window
          5. 9.2.1.2.5 Calculating the RESET Pullup Resistor
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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9.4.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.

  • Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor as near as possible to the VDD pin.
  • Place CCRST capacitor as close as possible to the CRST pin.
  • Place CCWD capacitor as close as possible to the CWD pin.
  • Place the pullup resistor on the RESET pin as close to the pin as possible.