ZHCSMU0D July   2009  – December 2020 TPS23753A

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Product Information
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Controller Section Only
    6. 7.6 Electrical Characteristics: PoE and Control
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Description
        1. 8.3.1.1  APD
        2. 8.3.1.2  BLNK
        3. 8.3.1.3  CLS
        4. 8.3.1.4  CS
        5. 8.3.1.5  CTL
        6. 8.3.1.6  DEN
        7. 8.3.1.7  FRS
        8. 8.3.1.8  GATE
        9. 8.3.1.9  RTN
        10. 8.3.1.10 VB
        11. 8.3.1.11 VC
        12. 8.3.1.12 VDD
        13. 8.3.1.13 VDD1
        14. 8.3.1.14 VSS
    4. 8.4 Device Functional Modes
      1. 8.4.1  Threshold Voltages
      2. 8.4.2  PoE Start-Up Sequence
      3. 8.4.3  Detection
      4. 8.4.4  Hardware Classification
      5. 8.4.5  Maintain Power Signature (MPS)
      6. 8.4.6  TPS23753A Operation
        1. 8.4.6.1 Start-Up and Converter Operation
        2. 8.4.6.2 PD Self-Protection
        3. 8.4.6.3 Converter Controller Features
      7. 8.4.7  Special Switching MOSFET Considerations
      8. 8.4.8  Thermal Considerations
      9. 8.4.9  FRS and Synchronization
      10. 8.4.10 Blanking – RBLNK
      11. 8.4.11 Current Slope Compensation
      12. 8.4.12 Adapter ORing
      13. 8.4.13 Protection
      14. 8.4.14 Frequency Dithering for Conducted Emissions Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Current Slope Compensation

Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer) current for stability at duty cycles near and over 50%. The TPS23753A has a maximum duty cycle limit of 78%, permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a narrower, 36-V to 57-V range. The TPS23753A provides a fixed internal compensation ramp that suffices for most applications. RS (see Figure 8-8) may be used if the internally provided slope compensation is not enough. It works with ramp current (IPK = ISL-EX, approximately 40 μA) that flows out of the CS pin when the MOSFET is on. The IPK specification does not include the approximately 3-μA fixed current that flows out of the CS pin.

Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp voltage / switching period); however, Electrical Characteristics: Controller Section Only specifies the slope peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full period, compute RS per Equation 7 where VSLOPE, DMAX, and ISL-EX are from Electrical Characteristics: Controller Section Only with voltages in mV, current in μA, and the duty cycle is unitless (for example, DMAX = 0.78).

Equation 7. GUID-CA85AA83-55B0-491A-B37D-DFD6ED4DFBE3-low.gif
GUID-E3CFC7DB-3F49-4A8D-8D3C-E382D8208D1F-low.gifFigure 8-8 Additional Slope Compensation

CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to appear at the CS pin. The TPS23753A has an internal pulldown on CS ( approximately 400 Ω maximum) while the MOSFET is OFF to reduce cycle-to-cycle carry-over voltage on CS.