SBVS124A November   2008  – May 2016 TPS2115A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 N-Channel MOSFETs
      2. 8.3.2 Cross-Conduction Blocking
      3. 8.3.3 Reverse-Conduction Blocking
      4. 8.3.4 Charge Pump
      5. 8.3.5 Current Limiting
      6. 8.3.6 Output Voltage Slew-Rate Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Auto-Switching Mode
      2. 8.4.2 Manual Switching Mode
  9. 9 Application and Information
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

5 Pin Configuration and Functions

PW Package
8-Pin TSSOP
Top View

Pin Functions

PIN Type DESCRIPTION
NAME NO.
D0 2 I TTL- and CMOS-compatible input pins. Each pin has a 1-μA pullup. The Truth Table shows the functionality of D0 and D1.
D1 3 I
GND 5 GND Ground
IN1 8 PWR Primary supply power-switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
IN2 6 PWR Secondary supply power-switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
ILIM 4 I A resistor RILIM from ILIM to GND sets the current limit IL to 500/RILIM.
OUT 7 O Power switch output
STAT 1 O Open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is Hi-Z (that is EN is equal to logic 0).