SLOS520A August   2007  – March 2016 TPA2013D1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Characteristics
    6. 7.6  Boost Converter DC Characteristics
    7. 7.7  Class D Amplifier DC Characteristics
    8. 7.8  AC Characteristics
    9. 7.9  Class D Amplifier AC Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifier
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Class-D Amplifier
      3. 9.3.3 Boost Converter
      4. 9.3.4 Operation With DACs and CODECs
      5. 9.3.5 Filter-Free Operation and Ferrite Bead Filters
      6. 9.3.6 Fixed Gain Settings
    4. 9.4 Device Functional Modes
      1. 9.4.1 Boost Converter Mode
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2013D1 With Differential Input Signal
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Setting the Boost Voltage
          2. 10.2.1.2.2 Inductor Selection
            1. 10.2.1.2.2.1 Surface Mount Inductors
            2. 10.2.1.2.2.2 TPA2013D1 Inductor Equations
          3. 10.2.1.2.3 Capacitor Selection
            1. 10.2.1.2.3.1 Surface Mount Capacitors
            2. 10.2.1.2.3.2 TPA2013D1 Capacitor Equations
          4. 10.2.1.2.4 Recommended Inductor and Capacitor Values by Application
          5. 10.2.1.2.5 Components Location and Selection
            1. 10.2.1.2.5.1 Decoupling Capacitors
            2. 10.2.1.2.5.2 Input Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Bypassing the Boost Converter
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Stereo Operation Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
      4. 10.2.4 LED Driver for Digital Still Cameras
      5. 10.2.5 Design Requirements
      6. 10.2.6 Detailed Design Procedure
      7. 10.2.7 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement
        1. 12.1.1.1 Trace Width
      2. 12.1.2 Pad Side
    2. 12.2 Layout Examples
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Device Nomenclature
        1. 13.1.2.1 Boost Terms
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

12 Layout

12.1 Layout Guidelines

12.1.1 Component Placement

Place all the external components close to the TPA2013D1 device. Placing the decoupling capacitors as close to the device as possible is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency

12.1.1.1 Trace Width

Recommended trace width at the solder balls is 75 μm to 100 μm to prevent solder wicking onto wider PCB traces.

For high current pins (SW, PGND, VOUT+, VOUT–, VCCIN, and VCCOUT) of the TPA2013D1, use 100-μm trace widths at the solder balls and at least 500-μm PCB traces to ensure proper performance and output power for the device.

For low current pins (IN–, IN+, SDd, SDb, GAIN, VCCFB, VDD) of the TPA2013D1, use 75-μm to 100-μm trace widths at the solder balls. Run IN– and IN+ traces side-by-side to maximize common-mode noise cancellation.

12.1.2 Pad Side

In making the pad size for the WCSP balls, use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 37 and Table 9 show the appropriate diameters for a WCSP layout.

TPA2013D1 ai_land2_los520.gif Figure 37. Land Pattern Dimensions

Table 9. Land Pattern Dimensions

SOLDER PAD
DEFINITIONS		 COPPER PAD SOLDER MASK
OPENING		 COPPER
THICKNESS		 STENCIL
OPENING		 STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)		 275 μm
(+0.0, –25 μm)		 375 μm
(+0.0, –25 μm)		 1 oz max (32 μm) 275 μm x 275 μm Sq.
(rounded corners)		 125 μm thick

NOTES:

  1. Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
  2. Recommend solder paste is Type 3 or Type 4.
  3. Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the intended application.
  4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
  5. Solder mask thickness should be less than 20 μm on top of the copper circuit pattern.
  6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control.
  7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces.

12.2 Layout Examples

TPA2013D1 TPA2015BGA_Layout.gif Figure 38. TPA2015BGA Layout
TPA2013D1 TPA2015QFN_Layout.gif Figure 39. TPA2015QFN Layout

12.3 Efficiency and Thermal Considerations

The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factors for the YZH and RGP packages are shown in Dissipation Ratings. Apply the same principles to both packages. Using the YZH package, and converting this to θJA:

Equation 8. TPA2013D1 eq8_theta_los520.gif

Given θJA of 80.64°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal dissipation of 0.317 W (VDD = 3.6 V, PO = 1.7 W), the maximum ambient temperature is calculated with Equation 9:

Equation 9. TPA2013D1 eq9_tam_los520.gif

Equation 9 shows that the calculated maximum ambient temperature is 124°C at maximum power dissipation under the above conditions. The TPA2013D1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier.