ZHCS009J
November 2010 – September 2021
PRODUCTION DATA
1
特性
2
应用
3
说明
3.1
功能方框图
3.2
系统器件图
4
Revision History
5
Device Comparison
5.1
Related Products
6
Terminal Configuration and Functions
6.1
Pin Diagrams
6.2
Signal Descriptions
6.2.1
Signal Descriptions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings – Commercial
7.3
ESD Ratings – Automotive
7.4
Recommended Operating Conditions
7.5
Power Consumption Summary
7.5.1
TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
7.5.2
Reducing Current Consumption
7.5.3
Current Consumption Graphs (VREG Enabled)
7.6
Electrical Characteristics
7.7
Thermal Resistance Characteristics
7.7.1
PFP PowerPAD Package
7.7.2
PZP PowerPAD Package
7.7.3
PN Package
7.7.4
PZ Package
7.8
Thermal Design Considerations
7.9
Debug Probe Connection Without Signal Buffering for the MCU
7.10
Parameter Information
7.10.1
Timing Parameter Symbology
7.10.2
General Notes on Timing Parameters
7.11
Test Load Circuit
7.12
Power Sequencing
7.12.1
Reset ( XRS) Timing Requirements
7.12.2
Reset ( XRS) Switching Characteristics
7.13
Clock Specifications
7.13.1
Device Clock Table
7.13.1.1
2806x Clock Table and Nomenclature (90-MHz Devices)
7.13.1.2
Device Clocking Requirements/Characteristics
7.13.1.3
Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
7.13.2
Clock Requirements and Characteristics
7.13.2.1
XCLKIN Timing Requirements – PLL Enabled
7.13.2.2
XCLKIN Timing Requirements – PLL Disabled
7.13.2.3
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
7.14
Flash Timing
7.14.1
Flash/OTP Endurance for T Temperature Material
7.14.2
Flash/OTP Endurance for S Temperature Material
7.14.3
Flash/OTP Endurance for Q Temperature Material
7.14.4
Flash Parameters at 90-MHz SYSCLKOUT
7.14.5
Flash/OTP Access Timing
7.14.6
Flash Data Retention Duration
8
Detailed Description
8.1
Overview
8.1.1
CPU
8.1.2
Control Law Accelerator (CLA)
8.1.3
Viterbi, Complex Math, CRC Unit (VCU)
8.1.4
Memory Bus (Harvard Bus Architecture)
8.1.5
Peripheral Bus
8.1.6
Real-Time JTAG and Analysis
8.1.7
Flash
8.1.8
M0, M1 SARAMs
8.1.9
L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
8.1.10
Boot ROM
8.1.10.1
Debug Boot
8.1.10.2
GetMode
8.1.10.3
Peripheral Pins Used by the Bootloader
8.1.11
Security
8.1.12
Peripheral Interrupt Expansion (PIE) Block
8.1.13
External Interrupts (XINT1 to XINT3)
8.1.14
Internal Zero Pin Oscillators, Oscillator, and PLL
8.1.15
Watchdog
8.1.16
Peripheral Clocking
8.1.17
Low-power Modes
8.1.18
Peripheral Frames 0, 1, 2, 3 (PFn)
8.1.19
General-Purpose Input/Output (GPIO) Multiplexer
8.1.20
32-Bit CPU-Timers (0, 1, 2)
8.1.21
Control Peripherals
8.1.22
Serial Port Peripherals
8.2
Memory Maps
8.3
Register Maps
8.4
Device Debug Registers
8.5
VREG, BOR, POR
8.5.1
On-chip VREG
8.5.1.1
Using the On-chip VREG
8.5.1.2
Disabling the On-chip VREG
8.5.2
On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
8.6
System Control
8.6.1
Internal Zero Pin Oscillators
8.6.2
Crystal Oscillator Option
8.6.3
PLL-Based Clock Module
8.6.4
USB and HRCAP PLL Module (PLL2)
8.6.5
Loss of Input Clock (NMI Watchdog Function)
8.6.6
CPU Watchdog Module
8.7
Low-power Modes Block
8.8
Interrupts
8.8.1
External Interrupts
8.8.1.1
External Interrupt Electrical Data/Timing
8.8.1.1.1
External Interrupt Timing Requirements
8.8.1.1.2
External Interrupt Switching Characteristics
8.9
Peripherals
8.9.1
CLA Overview
8.9.2
Analog Block
8.9.2.1
Analog-to-Digital Converter (ADC)
8.9.2.1.1
Features
8.9.2.1.2
ADC Start-of-Conversion Electrical Data/Timing
8.9.2.1.2.1
External ADC Start-of-Conversion Switching Characteristics
8.9.2.1.3
On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
8.9.2.1.3.1
ADC Electrical Characteristics
8.9.2.1.3.2
ADC Power Modes
8.9.2.1.3.3
Internal Temperature Sensor
8.9.2.1.3.3.1
Temperature Sensor Coefficient
8.9.2.1.3.4
ADC Power-Up Control Bit Timing
8.9.2.1.3.4.1
ADC Power-Up Delays
8.9.2.1.3.5
ADC Sequential and Simultaneous Timings
8.9.2.2
ADC MUX
8.9.2.3
Comparator Block
8.9.2.3.1
On-Chip Comparator/DAC Electrical Data/Timing
8.9.2.3.1.1
Electrical Characteristics of the Comparator/DAC
8.9.3
Detailed Descriptions
8.9.4
Serial Peripheral Interface (SPI) Module
8.9.4.1
SPI Master Mode Electrical Data/Timing
8.9.4.1.1
SPI Master Mode External Timing (Clock Phase = 0)
8.9.4.1.2
SPI Master Mode External Timing (Clock Phase = 1)
8.9.4.2
SPI Slave Mode Electrical Data/Timing
8.9.4.2.1
SPI Slave Mode External Timing (Clock Phase = 0)
8.9.4.2.2
SPI Slave Mode External Timing (Clock Phase = 1)
8.9.5
Serial Communications Interface (SCI) Module
8.9.6
Multichannel Buffered Serial Port (McBSP) Module
8.9.6.1
McBSP Electrical Data/Timing
8.9.6.1.1
McBSP Transmit and Receive Timing
8.9.6.1.1.1
McBSP Timing Requirements
8.9.6.1.1.2
McBSP Switching Characteristics
8.9.6.1.2
McBSP as SPI Master or Slave Timing
8.9.6.1.2.1
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
8.9.6.1.2.2
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
8.9.6.1.2.3
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
8.9.6.1.2.4
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
8.9.6.1.2.5
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
8.9.6.1.2.6
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
8.9.6.1.2.7
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
8.9.6.1.2.8
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
8.9.7
Enhanced Controller Area Network (eCAN) Module
8.9.8
Inter-Integrated Circuit (I2C)
8.9.8.1
I2C Electrical Data/Timing
8.9.8.1.1
I2C Timing Requirements
8.9.8.1.2
I2C Switching Characteristics
8.9.9
Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
8.9.9.1
ePWM Electrical Data/Timing
8.9.9.1.1
ePWM Timing Requirements
8.9.9.1.2
ePWM Switching Characteristics
8.9.9.2
Trip-Zone Input Timing
8.9.9.2.1
Trip-Zone Input Timing Requirements
8.9.10
High-Resolution PWM (HRPWM)
8.9.10.1
HRPWM Electrical Data/Timing
8.9.10.1.1
High-Resolution PWM Characteristics
8.9.11
Enhanced Capture Module (eCAP1)
8.9.11.1
eCAP Electrical Data/Timing
8.9.11.1.1
Enhanced Capture (eCAP) Timing Requirement
8.9.11.1.2
eCAP Switching Characteristics
8.9.12
High-Resolution Capture Modules (HRCAP1 to HRCAP4)
8.9.12.1
HRCAP Electrical Data/Timing
8.9.12.1.1
High-Resolution Capture (HRCAP) Timing Requirements
8.9.13
Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
8.9.13.1
eQEP Electrical Data/Timing
8.9.13.1.1
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
8.9.13.1.2
eQEP Switching Characteristics
8.9.14
JTAG Port
8.9.15
General-Purpose Input/Output (GPIO) MUX
8.9.15.1
GPIO Electrical Data/Timing
8.9.15.1.1
GPIO Output Timing
8.9.15.1.1.1
General-Purpose Output Switching Characteristics
8.9.15.1.2
GPIO Input Timing
8.9.15.1.2.1
General-Purpose Input Timing Requirements
8.9.15.1.3
Sampling Window Width for Input Signals
8.9.15.1.4
Low-Power Mode Wakeup Timing
8.9.15.1.4.1
IDLE Mode Timing Requirements
8.9.15.1.4.2
IDLE Mode Switching Characteristics
8.9.15.1.4.3
STANDBY Mode Timing Requirements
8.9.15.1.4.4
STANDBY Mode Switching Characteristics
8.9.15.1.4.5
HALT Mode Timing Requirements
8.9.15.1.4.6
HALT Mode Switching Characteristics
8.9.16
Universal Serial Bus (USB)
8.9.16.1
USB Electrical Data/Timing
8.9.16.1.1
USB Input Ports DP and DM Timing Requirements
8.9.16.1.2
USB Output Ports DP and DM Switching Characteristics
9
Applications, Implementation, and Layout
9.1
TI Reference Design
10
Device and Documentation Support
10.1
Device and Development Support Tool Nomenclature
10.2
Tools and Software
10.3
Documentation Support
10.4
支持资源
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
术语表
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Information
封装选项
机械数据 (封装 | 引脚)
PN|80
MTQF010B
PZ|100
MTQF013A
散热焊盘机械数据 (封装 | 引脚)
PZ|100
QFND428
订购信息
zhcs009j_oa
zhcs009j_pm
8.1
Overview