ZHCSGV3G June 2009 – January 2017 TMS320C6748
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01E1 6000 | UPPID | uPP Peripheral Identification Register |
0x01E1 6004 | UPPCR | uPP Peripheral Control Register |
0x01E1 6008 | UPDLB | uPP Digital Loopback Register |
0x01E1 6010 | UPCTL | uPP Channel Control Register |
0x01E1 6014 | UPICR | uPP Interface Configuration Register |
0x01E1 6018 | UPIVR | uPP Interface Idle Value Register |
0x01E1 601C | UPTCR | uPP Threshold Configuration Register |
0x01E1 6020 | UPISR | uPP Interrupt Raw Status Register |
0x01E1 6024 | UPIER | uPP Interrupt Enabled Status Register |
0x01E1 6028 | UPIES | uPP Interrupt Enable Set Register |
0x01E1 602C | UPIEC | uPP Interrupt Enable Clear Register |
0x01E1 6030 | UPEOI | uPP End-of-Interrupt Register |
0x01E1 6040 | UPID0 | uPP DMA Channel I Descriptor 0 Register |
0x01E1 6044 | UPID1 | uPP DMA Channel I Descriptor 1 Register |
0x01E1 6048 | UPID2 | uPP DMA Channel I Descriptor 2 Register |
0x01E1 6050 | UPIS0 | uPP DMA Channel I Status 0 Register |
0x01E1 6054 | UPIS1 | uPP DMA Channel I Status 1 Register |
0x01E1 6058 | UPIS2 | uPP DMA Channel I Status 2 Register |
0x01E1 6060 | UPQD0 | uPP DMA Channel Q Descriptor 0 Register |
0x01E1 6064 | UPQD1 | uPP DMA Channel Q Descriptor 1 Register |
0x01E1 6068 | UPQD2 | uPP DMA Channel Q Descriptor 2 Register |
0x01E1 6070 | UPQS0 | uPP DMA Channel Q Status 0 Register |
0x01E1 6074 | UPQS1 | uPP DMA Channel Q Status 1 Register |
0x01E1 6078 | UPQS2 | uPP DMA Channel Q Status 2 Register |