SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

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Manual Reset (MR) Input

The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR with pulse duration longer than tMR_PW will cause the reset output to assert. After MR returns to a logic high
(VMR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.

The minimum duration for which MR is held under VMR_L must be at least 1% of tMR_tD. Otherwise, the effective reset delay will be shorter roughly by the difference between 1% of tMR_tD and the actual MR pulse width. For large capacitor based delays this difference could be noticeable unless care is taken to lengthen the MR pulse width.

MR is internally connected to VDD through a pull-up resistor RMR shown in Section 8.2. If the logic signal controlling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND. VMR should not be higher than VDD voltage.

GUID-20200918-CA0I-L3DL-HDJD-BNHX22JZCTZ9-low.gif Figure 8-4 Timing Diagram MR and RESET