SBVS151F December   2010  – April 2017 TLV705 , TLV705P

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Undervoltage Lockout (UVLO)
      3. 7.3.3 Start-Up Current
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Transient Response
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Power Dissipation and Junction Temperature
    5. 10.5 Estimating Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Mounting

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Detailed Description

Overview

The TLV705 and TLV705P series of devices belong to a family of next-generation value low-dropout (LDO) voltage regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. This performance, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, makes these devices ideal for RF portable applications. This family of regulators offers sub-band-gap output voltages down to 0.7 V, current limit, and thermal protection, and are specified from –40°C to +125°C. The TLV705P provides an active pulldown circuit to quickly discharge the outputs.

Functional Block Diagrams

TLV705 TLV705P fbd_705xx_bvs151.gif Figure 26. TLV705 Series
TLV705 TLV705P fbd_705xxp_bvs151.gif Figure 27. TLV705P Series

Feature Description

Internal Current Limit

The internal current limits of the TLV705 series help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and can be measured as VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When the device cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown; see Power Dissipation and Junction Temperature for more details.

The PMOS pass element in the TLV705 has a built-in body diode that conducts current when the voltage at VOUT exceeds the voltage at VIN. This current is not limited, so if extended reverse voltage operation is anticipated, TI recommends external limiting to 5% of the rated output current.

Undervoltage Lockout (UVLO)

The TLV705 uses an UVLO circuit to keep the output shut off until the internal circuitry is operating properly.

Start-Up Current

The TLV705 uses a unique start-up architecture that creates a constant start-up time regardless of the output capacitor. The start-up current is given by Equation 1. Equation 1 shows that start-up current is directly proportional to COUT.

Equation 1. ISTARTUP = COUT (μF) × 0.06 (Vμs) + ILOAD (mA)

The output voltage ramp rate is independent of COUT and the load current, and has a typical value of 0.06 V/μs.

The TLV705 automatically adjusts the soft-start current to supply both the load current and the current to charge COUT. For example, if ILOAD = 0 mA upon enabling the LDO, then ISTARTUP = 1 μF × 0.06 Vμs + 0 mA = 60 mA, which is the current that charges the output capacitor.

However, if ILOAD = 200 mA, then ISTARTUP = 1 μF × 0.06 V / μs + 200 mA = 260 mA, which is the required current to charge the output capacitor and supply the load current.

If the output capacitor and load increase such that the start-up current exceeds the output current limit, the start-up current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and
IOUT = 200 mA, then 10 μF × 0.06 V / μs + 200 mA = 800 mA is not supplied and is instead clamped at 400 mA.

Dropout Voltage

The TLV705 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device functions as a resistor in dropout.

As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 13 in the Typical Characteristics.

Shutdown

The enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relatively lower value of voltage required to turn the LDO on can power the device with the GPIO of recent processors with a GPIO voltage lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the VIN pin. The TLV705P version has internal active pulldown circuitry that discharges the output with a time constant of:

Equation 2. τ = (120 × RL) / (120 + RL) × COUT

where

  • RL = load resistance
  • COUT = output capacitor

Device Functional Modes

Normal Operation

The device regulates to the nominal output voltage under the following conditions:

  • The input voltage is greater than the nominal output voltage added to the dropout voltage.
  • The output current is less than the current limit.
  • The input voltage is greater than the UVLO voltage.

Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the LDO. Line or load transients in dropout can result in large output voltage deviations.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODE PARAMETER
VIN IOUT
Normal mode VIN > VOUT (nom) + VDO IOUT < ICL
Dropout mode VIN < VOUT (nom) + VDO IOUT < ICL
Current limit VIN > UVLO IOUT > ICL