SBOS858 April   2017 TLV171-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV171-Q1
    5. 6.5 Thermal Information: TLV2171-Q1
    6. 6.6 Thermal Information: TLV4171-Q1
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Capacitive Load and Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Common-Mode Voltage Range
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Electrical Overstress
    2. 8.2 Typical Application
      1. 8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Layout

Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. See Circuit Board Layout Techniques for detailed information.
  • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. As shown in Figure 33, keeping RF and RG close to the inverting input minimizes parasitic capacitance.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

Layout Example

TLV171-Q1 TLV2171-Q1 TLV4171-Q1 layout_example_bos620.gif Figure 33. Operational Amplifier Board Layout for Noninverting Configuration