SLLSE75B May   2011  – July 2016 TLK10002

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  10-Gbps Power Characteristics - 1.0 V
    6. 7.6  10-Gbps Power Characteristics - 1.5 V
    7. 7.7  10-Gbps Power Characteristics - 1.8 V
    8. 7.8  Transmitter and Receiver Characteristics
    9. 7.9  MDIO Timing Requirements
    10. 7.10 JTAG Timing Requirements
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Side Receiver Jitter Tolerance
      2. 8.3.2  Lane Alignment Scheme
      3. 8.3.3  Lane Alignment Components
      4. 8.3.4  Lane Alignment Operation
      5. 8.3.5  Channel Synchronization
      6. 8.3.6  Line Rate, SERDES PLL Settings, and Reference Clock Selection
      7. 8.3.7  Clocking Architecture
      8. 8.3.8  Loopback Modes
      9. 8.3.9  Deep Remote Loopback
      10. 8.3.10 Shallow Remote Loopback and Serial Retime
      11. 8.3.11 Deep Local Loopback
      12. 8.3.12 Shallow Local Loopback
      13. 8.3.13 Test Pattern Generation and Verification
      14. 8.3.14 Latency Measurement Function
      15. 8.3.15 Power-Down Mode
      16. 8.3.16 High Speed CML Output
      17. 8.3.17 High Speed Receiver
      18. 8.3.18 Loss of Signal Indication (LOS)
      19. 8.3.19 MDIO Management Interface
      20. 8.3.20 MDIO Protocol Timing
      21. 8.3.21 Clause 22 Indirect Addressing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transmit (Low Speed to High Speed) Data Path
      2. 8.4.2 Receive (High Speed to Low Speed) Data Path
      3. 8.4.3 1:1 Retime Mode
    5. 8.5 Programming
      1. 8.5.1 Power Sequencing Guidelines
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Initialization Setup
      1. 9.3.1 4:1 Mode (9.8304 Gbps on HS Side, 2.4576 Gbps Per Lane on LS Side)
      2. 9.3.2 2:1 Mode (9.8304 Gbps on HS Side, 4.9152 Gbps Per Lane on LS Side, Only Lanes 0 and 1 on LS Side Active)
      3. 9.3.3 1:1 Mode (4.9152 Gbps on HS Side, 4.9152Gbps on LS side, Only Lane 0 on LS Side Active)
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 AC Coupling
      2. 11.1.2 TLK10002 Clocks: REFCLK, CLKOUT - General Information
      3. 11.1.3 External Clock Connections
      4. 11.1.4 TLK10002 Control Pins and Interfaces
        1. 11.1.4.1 MDIO Interface
        2. 11.1.4.2 JTAG Interface
        3. 11.1.4.3 Unused Pins
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Detailed Description

Overview

The TLK10002 is a versatile high-speed transceiver device that is designed to perform various physical layer functions. It is equipped with a number of functions and testability features that make it easy to integrate the device in high-speed communications systems, especially in wireless infrastructure. The details of those features are discussed in Feature Description.

A simplified block diagram of the TLK10002 device is shown in the Functional Block Diagram section for Channel A which is identical to Channel B. This low-power transceiver consists of two serializer/deserializer (SERDES) blocks, one on the low speed side and the other on the high speed side. The core logic block that lies between the two SERDES blocks carries out all the logic functions including channel synchronization, lane alignment, 8B/10B encoding/decoding, as well as test pattern generation and verification.

The TLK10002 provides a management data input/output (MDIO) interface as well as a JTAG interface for device configuration, control, and monitoring. Detailed description of the TLK10002 pin functions is provided in Pin Configuration and Functions.

Functional Block Diagram

TLK10002 bd_llse75.gif

Feature Description

High-Speed Side Receiver Jitter Tolerance

The peak-to-peak total jitter tolerance for the RP3 receiver is 0.65 UI. This total jitter is composed of three components; deterministic jitter, random jitter, and an additional sinusoidal jitter.

The deterministic jitter tolerance is 0.37 UI minimum. The sum of deterministic and random jitter is 0.55 UI minimum. The additional sinusoidal jitter which the receiver must tolerate will have frequencies and amplitudes conforming to the mask presented in the Figure 9 and Table 1.

TLK10002 OBSAI_msk_llse75.gif Figure 9. OBSAI Sinusoidal Jitter Mask

Table 1. Sinusoidal Jitter Mask Values

Frequency
(MBaud)
f1
(kHz)
f2
(kHz)
UI 1pp UI 2pp
768 5.4 460.8 0.1 8.5
1536 10.9 921.6 0.1 8.5
3072 21.8 1843.2 0.1 8.5
6144 36.9 3686 0.05 5
9830.4 59 5897.6 0.05 5

Lane Alignment Scheme

Lower rate multi-lane serial signals per channel must be byte aligned and lane aligned such that high-speed multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10002 implements a special lane alignment scheme on the low-speed (LS) side.

During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored.

Lane alignment completes successfully when the LS receiver asserts a Link Status OK signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10002 sends out the Link Status OK signals through the LS_OK_OUT_A/B output pins, and monitors the Link Status OK signals from the link partner device through the LS_OK_IN_A/B input pins. If the link partner device does not need the TLK10002 Lane Align Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A/B can be tied high on the application board.

The lane alignment scheme is activated under any of the following conditions:

  • Device/System power up (after configuration/provisioning)
  • Loss of channel synchronization assertion on any enabled LS lane
  • Loss of signal assertion on any enabled LS lane
  • LS SERDES PLL Lock indication deassertion
  • After device configuration change
  • After software determined LS 8B/10B decoder error rate threshold exceeded
  • After device reset is deasserted
  • Anytime the LS receiver deasserts Link Status OK.
  • Presence of reoccurring higher level / protocol framing errors

The block diagram of the lane alignment scheme is shown in Figure 10.

TLK10002 lane_align_llse75.gif Figure 10. Block Diagram of the Lane Alignment Scheme

Lane Alignment Components

  • Lane Alignment Master (LAM)
    • Responsible for generating proprietary LS lane alignment initialization pattern
    • Resides in the TLK10002 LS receiver (one instance in Channel A, one instance in Channel B)
      • Responsible for bringing up LS receive link for the data sent from the TLK10002 to a link partner device
      • Monitors the LS_OK_IN_A/B pins for Link Status OK signals sent from the Lane Alignment Slave (LAS) of the link partner device
    • Resides in the link partner device (one instance in Channel A, one instance in Channel B)
      • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10002
      • Monitors the Link Status OK signals sent from the LS_OK_OUT_A/B pins of the Lane Alignment Slave (LAS) of the TLK10002
  • Lane Alignment Slave (LAS)
    • Responsible for monitoring the LS lane alignment initialization pattern
    • Performs channel synchronization per lane (2 or 4 lanes) through byte rotation
    • Performs lane alignment and realignment of bytes across lanes
    • Resides in the TLK10002 LS receiver (one instance in Channel A, one instance in Channel B)
      • Generates the Link Status OK signal for the LAM on the link partner device
    • Resides in the link partner device (one instance in Channel A, one instance in Channel B)
      • Generates the Link Status OK signal for the LAM on the TLK10002 device.

Lane Alignment Operation

During lane alignment, the LS transmitter (LAM) sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters:

/K28.5/ (CTL=1, Data=0xBC)

Repeat the following sequence of 12 characters four times:

/D30.5/ (CTL=0, Data=0xBE)
/D23.6/ (CTL=0, Data=0xD7)
/D3.1/ (CTL=0, Data=0x23)
/D7.2/ (CTL=0, Data=0x47)
/D11.3/ (CTL=0, Data=0x6B)
/D15.4/ (CTL=0, Data=0x8F)
/D19.5/ (CTL=0, Data=0xB3)
/D20.0/ (CTL=0, Data=0x14)
/D30.2/ (CTL=0, Data=0x5E)
/D27.7/ (CTL=0, Data=0xFB)
/D21.1/ (CTL=0, Data=0x35)
/D25.2/ (CTL=0, Data=0x59)

The above 49-character sequence is repeated until LS_OK_IN_A/B is asserted. Once LS_OK_IN_A/B is asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately.

The TLK10002 performs lane alignment across the lanes similar in fashion to the IEEE 802.3ae-2002 (XAUI) specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state machine is shown in Figure 11. The comma (K28.5) character is used for lane to lane alignment instead of XAUI’s /A/ character.

Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that the LS_OK_IN_A/B signal is asserted, normal system traffic is carried instead of the proprietary lane alignment pattern.

Channel Synchronization is performed during lane alignment and normal system operation.

TLK10002 state_mach_llse75.gif Figure 11. Lane Alignment State Machine

Channel Synchronization

The TLK10002 performs channel synchronization per lane as per IEEE802.3-2002 Figure 36–9 Synchronization state diagram and as shown in the flowchart of Figure 12.

TLK10002 ch_flow_llse75.gif Figure 12. Channel Synchronization Flowchart

Line Rate, SERDES PLL Settings, and Reference Clock Selection

The TLK10002 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low-speed and high-speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications.

The external differential reference clock has a large operating frequency range allowing support for many different applications. The reference clock frequency must be within 200 PPM of the incoming serial data rate (±100 PPM of nominal data rate), and have less than 40 ps of jitter. Table 2 shows a summary of line rates and reference clock frequencies used for CPRI/OBSAI for the 1:1, 2:1, and 4:1 operation modes.

Table 2. Specific Line Rate Selection for the 1:1 Operation Mode

LOW-SPEED SIDE HIGH-SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
4915.2 20 Full 122.88 4915.2 20 Half 122.88
3840 12.5 Full 153.6 3840 12.5 Half 153.6
3072 10 Full 153.6 3072 10 Half 153.6
2457.6 8/10 Full 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88
1920 12.5 Half 153.6 1920 12.5 Quarter 153.6
1536 10 Half 153.6 1536 10 Quarter 153.6
1228.8 8/10 Half 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88

Table 3. Specific Line Rate Selection for the 2:1 Operation Mode

LOW-SPEED SIDE HIGH-SPEED SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
4915.2 20 Full 122.88 9830.4 20 Full 122.88
3840 12.5 Full 153.6 7680 12.5 Full 153.6
3072 10 Full 153.6 6144 10 Full 153.6
2457.6 8/10 Full 153.6/122.88 4915.2 16/20 Half 153.6/122.88
1920 12.5 Half 153.6 3840 12.5 Half 153.6
1536 10 Half 153.6 3072 10 Half 153.6
1228.8 8/10 Half 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88
768 10 Quarter 153.6 1536 10 Quarter 153.6
614.4 8/10 Quarter 153.6/122.88 1228.8 16/20 Eighth 153.6/122.88

Table 4. Specific Line Rate Selection for the 4:1 Operation Mode

LOW-SPEED SIDE HIGH SPEED-SIDE
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER
RATE REFCLKP/N
(MHz)
2457.6 8/10 Full 153.6/122.88 9830.4 16/20 Full 153.6/122.88
1536 10 Half 153.6 6144 10 Full 153.6
1228.8 8/10 Half 153.6/122.88 4915.2 16/20 Half 153.6/122.88
768 10 Quarter 153.6 3072 10 Half 153.6
614.4 8/10 Quarter 153.6/122.88 2457.6 16/20 Quarter 153.6/122.88

Table 2, Table 3, and Table 4 indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6 MHz and 122.88 MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. For each channel, the low-speed side and the high-speed side SERDES use the same reference clock frequency. Note that Channel A and B are independent and their application rates and references clocks are separate.

For other line rates not shown in Table 3 and Table 4, valid reference clock frequencies can be selected with the help of the information provided in Table 5 and Table 6 for the low-speed side and high-speed side SERDES. The reference clock frequency has to be the same for the two SERDES and must be within the specified valid ranges for different PLL multipliers.

Table 5. Line Rate and Reference Clock Frequency Ranges for the Low-Speed Side SERDES

SERDES PLL
MULTIPLIER (MPY)
REFERENCE CLOCK
(MHz)
FULL RATE
(Gbps)
HALF RATE
(Gbps)
QUARTER RATE
(Gbps)
MIN MAX MIN MAX MIN MAX MIN MAX
4 250 425 2 3.4 1 1.7 0.5 0.85
5 200 425 2 4.25 1 2.125 0.5 1.0625
6 166.667 416.667 2 5 1 2.5 0.5 1.25
8 125 312.5 2 5 1 2.5 0.5 1.25
10 122.88 250 2.4576 5 1.2288 2.5 0.6144 1.25
12 122.88 208.333 2.94912 5 1.47456 2.5 0.73728 1.25
12.5 122.88 200 3.072 5 1.536 2.5 0.768 1.25
15 122.88 166.667 3.6864 5 1.8432 2.5 0.9216 1.25
20 122.88 125 4.9152 5 2.4576 2.5 1.2288 1.25
RateScale: Full Rate = 0.5, Half Rate = 1, Quarter Rate = 2

Table 6. Line Rate and Reference Clock Frequency Ranges for the High-Speed Side SERDES

SERDES PLL
MULTIPLIER (MPY)
REFERENCE CLOCK
(MHz)
FULL RATE
(Gbps)
HALF RATE
(Gbps)
QUARTER RATE
(Gbps)
EIGHTH RATE
(Gbps)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
4 375 425 6 6.8 3 3.4 1.5 1.7
5 300 425 6 8.5 3 4.25 1.5 2.125 1 1.0625
6 250 416.667 6 10 3 5 1.5 2.5 1 1.25
8 187.5 312.5 6 10 3 5 1.5 2.5 1 1.25
10 150 250 6 10 3 5 1.5 2.5 1 1.25
12 125 208.333 6 10 3 5 1.5 2.5 1 1.25
12.5 153.6 200 7.68 10 3.84 5 1.92 2.5 1 1.25
15 122.88 166.667 7.3728 10 3.6864 5 1.8432 2.5 1 1.25
16 122.88 156.25 7.864 10 3.932 5 1.966 2.5 1 1.25
20 122.88 125 9.8304 10 4.9152 5 2.4576 2.5 1.2288 1.25
RateScale: Full Rate = 0.25, Half Rate = 0.5, Quarter Rate = 1, Eighth Rate = 2

For example, in the 2:1 operation mode, if the low-speed side line rate is 1.987 Gbps, the high-speed side line rate is 3.974 Gbps. The following steps can be taken to make a reference clock frequency selection:

  1. Determine the appropriate SERDES rate modes that support the required line rates. Table 5 shows that the 1.987 Gbps line rate on the low-speed side is only supported in the half rate mode (RateScale = 1). Table 6 shows that the 3.974 Gbps line rate on the high-speed side is only supported in the half rate mode (RateScale = 0.5).
  2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference clock frequencies using the formula:
  3. Reference Clock Frequency = (LineRate x RateScale)/MPY

    The computed reference clock frequencies are shown in Table 7 along with the valid minimum and maximum frequency values.

  4. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 7.
  5. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the reference clock frequencies in Table 7 can be selected: 397.4 MHz, 331.167 MHz, 248.375 MHz, 198.7 MHz, 165.583 MHz, 158.96 MHz, and 132.467 MHz.

Table 7. Reference Clock Frequency Selection Example

LOW-SPEED SIDE SERDES HIGH-SPEED SIDE SERDES
SERDES PLL
MULTIPLIER
REFERENCE CLOCK FREQUENCY
(MHz)
SERDES PLL
MULTIPLIER
REFERENCE CLOCK FREQUENCY
(MHz)
COMPUTED MIN MAX COMPUTED MIN MAX
4 496.750 250 425 4 496.750 250 425
5 397.400 200 425 5 397.400 200 425
6 331.167 166.667 416.667 6 331.167 166.667 416.667
8 248.375 125 312.5 8 248.375 125 312.5
10 198.700 122.88 250 10 198.700 122.88 250
12 165.583 122.88 208.333 12 165.583 122.88 208.333
12.5 158.960 122.88 200 12.5 158.960 122.88 200
15 132.467 122.88 166.667 15 132.467 122.88 166.667
20 99.350 122.88 125 20 99.350 122.88 125

Clocking Architecture

A simplified clocking architecture for the TLK10002 is captured in Figure 13. Each channel (Channel A or Channel B) has an option of operating with a differential reference clock provided either on pins REFCLK0P/N or REFCLK1P/N. The choice is made either through MDIO or through REFCLKA_SEL and REFCLKB_SEL pins. The reference clock frequencies for those two clock inputs can be different as long as they fall under the valid ranges shown in Table 6. For each channel, the low-speed side SERDES, high-speed side SERDES and the associated part of the digital core operate from the same reference clock.

The clock and data recovery (CDR) function of the high-speed side receiver recovers the clock from the incoming serial data. The high-speed side SERDES makes available two versions of clocks for further processing:

  1. HS_RXBCLK_A/B: recovered byte clock synchronous with incoming serial data and with a frequency matching the incoming line rate divided by 20.
  2. VCO_CLOCK_A/B_DIV2: VCO frequency divided by 2. (VCO frequency = REFCLK x PLL Multiplier).

The above-mentioned clocks can be output through the differential pins, CLKOUTAP/N and CLKOUTBP/N, with optional frequency division ratios of 1, 2, 4, 5, 8, 10, 16, 20, or 25. The clock output options are software controlled through the MDIO interface register bits 1.3:2, and 1.7:4. The maximum CLKOUT frequency is 500 MHz.

TLK10002 clocking_llse75.gif Figure 13. Clocking Architecture

Loopback Modes

The TLK10002 provides two high-speed side (remote) and two low-speed side (local) loopback modes for self-test and system diagnostic purposes. The details of those loopback modes are discussed below.

Deep Remote Loopback

The deep remote loopback is as shown Figure 14 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the high-speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the entire receive data path excluding the CML driver and receive sense amps on the low-speed side SERDES, returned through the entire transmit data path and sent out through the high-speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).

The low-speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. See MDIO register bit 6.7 in Table 21 for more information. The OUTA*P/N and OUTB*P/N pins must be correctly terminated.

The link partner connected through INA*P/N or INB*P/N pins must be electrically idle at differential zero with P and N signals at the same voltage. The TLK10002 device needs some time for lane alignment before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local LS_OK_OUT_A/B.

TLK10002 loopback1_llse75.gif Figure 14. Deep Remote Loopback

Shallow Remote Loopback and Serial Retime

The shallow remote loopback is as shown in Figure 15 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the high-speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the receive data path and looped back before the low-speed SERDES, returned through the transmit data path and sent out through the high-speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).

The low-speed side transmit path SERDES can be optionally enabled or disabled but the PLL needs to be enabled to provide the required clock.

The low-speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. The OUTA*P/N and OUTB*P/N pins must be correctly terminated. The TLK10002 device needs some time for lane alignment before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local LS_OK_OUT_A/B.

This loopback mode can be used for high-speed serial retime operation.

TLK10002 loopback2_llse75.gif Figure 15. Shallow Remote Loopback

Deep Local Loopback

The deep local loopback mode is as shown in Figure 16 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the low-speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit data path excluding the CML driver, returned through the entire receive data path and sent out through the low-speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time for lane alignment before passing traffic. The high-speed side outputs on HSTXAP/N or HSTXBP/N pins are available for monitoring.

TLK10002 loopback3_llse75.gif Figure 16. Deep Local Loopback

Shallow Local Loopback

The shallow local loopback mode is as shown in Figure 17 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the low-speed side SERDES pins (INA x P/N or INB x P/N), traverses the entire transmit data path excluding the high-speed side SERDES, returned through the entire receive data path and sent out through the low-speed side SERDES pins (OUTA x P/N or OUTB x P/N). The TLK10002 device needs some time for lane alignment before passing traffic. The high-speed side outputs on HSTXAP/N or HSTXBP/N pins are available for monitoring.

TLK10002 loopback4_llse75.gif Figure 17. Shallow Local Loopback

Test Pattern Generation and Verification

The TLK10002 has an extensive suite of built-in test functions to support system diagnostic requirements. Each channel has sets of internal test pattern generators and verifiers.

Several patterns can be selected through the MDIO interface that offer extensive test coverage. The low-speed side supports generation and verification of pseudo-random bit sequence (PRBS) 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High-frequency (HF), Low-frequency (LF), Mixed-frequency (MF), and continuous random test pattern (CRPAT) long/short pattern generation and verification as defined in Annex 48A of the IEEE Standard 802.3ae-2002. Use of CRPAT verifier requires checking TPsync (MDIO register bit F.15).

The TLK10002 provides two pins: PRBSEN and PRBS_PASS, for additional and easy control and monitoring of PRBS pattern generation and verification. When the PRBSEN is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high-speed and low-speed sides of both channels. This signal is logically OR’d with an MDIO register bits B.7:6 and B.13:12.

PRBS 231-1 is selected by default, and can be changed through MDIO.

When PRBS test is enabled (PRBSEN=1):

  • PRBS_PASS=1 indicates that PRBS pattern reception is error free.
  • PRBS_PASS=0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed), and the lane (for low-speed side) that this signal refers to is chosen through MDIO register bit 0.3:0.

Latency Measurement Function

The TLK10002 includes a latency measurement function to support CPRI and OBSAI base station applications. There are two start and two stop locations for the latency counter as shown in Figure 18 for Channel A. The start and stop locations are selectable through MDIO register bits 0x16.7 and 0x16.6 respectively. The elapsed time from a comma detected at an assigned counter start location of a particular channel to a comma detected at an assigned counter stop location of the same channel is measured and reported through the MDIO interface. The function operates on one channel at a time. The following three control characters (containing commas) are monitored:

  1. K28.1 (control = 1, data = 0x3C)
  2. K28.5 (control = 1, data = 0xBC)
  3. K28.7 (control = 1, data = 0xFC).

The first comma found at the assigned counter start location starts up the latency counter. The first comma detected at the assigned counter stop location stops the latency counter. The 20-bit latency counter result of this measurement is readable through the MDIO interface through register bits 0x17.3:0 and 0x18.15:0. The accuracy of the measurement is a function of the serial bit rate at which the channel being measured is operating. The register will return a value of 0xFFFF if the duration between transmit and receive comma detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit results counter is read. The counter will return zero in cases where a transmit comma was never detected (indicating the results counter never began counting).

TLK10002 TX_RX_loca_llse75.gif Figure 18. Location of TX and RX Comma Character Detection (Only Channel A Shown)

In high-speed side SERDES full rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the serial bit rate divided by 4. In quarter rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the serial bit rate divided by 2. In eighth rate mode, the latency measurement function runs off of a clock whose rate is equal to the serial bit rate.

The latency measurement does not include the low-speed side transmit SERDES blocks contribution as well as part of the channel synchronization block. The latency introduced by these blocks can be estimated to be up to (18 + 10) x N high-speed side unit intervals (UIs), where the multiplex factor N is equal to 2 (in 2:1 mode) or 4 (in 4:1 mode). The latency measurement also doesn’t account for the low-speed side receive SERDES contribution which is estimated to be up to 20 x N high-speed side UIs. The latency contributions of various sections of the TLK10002 device are shown in Figure 17. Overall, the transmit data path full rate latency contribution is estimated to be between 462UI and 602UI for the 2:1 mode, and between 798UI and 1058UI for the 4:1 mode. The respective numbers for the receive data path are between 300UI and 403UI for the 2:1 mode and between 440UI and 623UI for the 4:1 mode.

The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period. The measurement clock can be divided down if a longer duration measurement is required, in which case the accuracy of the measurement is accordingly reduced. The high-speed latency measurement clock is divided by either 1, 2, 4, or 8 via register 0x16 bits 5:4. The measurement clock used is always selected by the channel under test. The high-speed latency measurement clock may only be used when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off of the recovered byte clock for the channel under test (and gives a latency measurement clock frequency equal to the serial bit rate divided by 20) through register 0x16 bit 2 (where the register 0x16 bits 5:4 divider value setting is ignored).

The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 8, and assumes the latency measurement clock is not divided down per user selection (division is required to measure a duration greater than 682 µs). For each division of two in the measurement clock, the accuracy is also reduced by a factor of two.

To use the latency measurement feature, follow this procedure:

  1. Provision stopwatch clock frequency (divide by N), channel select, and start or stop location through the LATENCY_MEASURE_CONTROL register (0x16) and enable the stopwatch clock. In choosing a divider, note that the frequency of the divided clock must not be slower than the internal high speed byte clock.
  2. Read status register 18.15:0 to clear and reset delay stopwatch.
  3. Send comma pattern (after lane alignment has been achieved and the link status is OK).
  4. Poll bit 17.4 until it is asserted.
  5. Read the start and stop comma location and the lane align pointer values indicating relative skew among the lanes of the selected channel. These may need to be processed together with the stopwatch counter values for more accurate latency analysis.
  6. Read counter status values. The four MSB in bits 17.3:0 should be read first, followed by the LSBs in 18.15:0. If the value is 0, then the comma was never detected. If the value is at its maximum, the delay was too long for the counter’s range. If this happens, decrease the measurement clock frequency and repeat the measurement.
  7. Once the lower 16 bits at 18.15:0 are read, the delay stopwatch is reset and 17.4 is cleared. The comma location latch registers are cleared too. To do a new measurement, start again from step (3) for the same channel and from step (1) if a different channel is desired.
  8. Take the counter value and multiply it with the latency clock period divided by 2. This will provide the absolute latency period.

TLK10002 latency_var2_llse75.gif

NOTE:

Latency numbers represent no external skew between lanes. External lane skew will increase overall latency. TX Datapath latency includes 20xN UI of variance due to deserialization and channel sync.
Figure 19. Latency Variance and Contributions (Only Channel A Shown)

Table 8. CPRI/OBSAI Latency Measurement Function Accuracy
(Undivided Measurement Clock)

LINE RATE
(Gbps)
RATE LATENCY CLOCK FREQUENCY
(GHz)
ACCURACY
(± ns)
1.2288 Eighth 1.2288 0.8138
1.536 Quarter 0.768 1.302
2.4576 Quarter 1.2288 0.8138
3.072 Half 0.768 1.302
3.84 Half 0.96 1.0417
4.9152 Half 1.2288 0.8138
6.144 Full 0.768 1.302
7.68 Full 0.96 1.0417
9.8304 Full 1.2288 0.8138

Power-Down Mode

The TLK10002 can be put in power down either through device inputs pins or through MDIO control register (1.15).

PDTRXA_N: Active low, powers down channel A.
PDTRXB_N: Active low, powers down channel B.

The MDIO management serial interface remains operational when in register-based, power-down mode (1.15 asserted for both channels), but status bits may not be valid since the clocks are disabled. The low-speed side and high-speed side SERDES outputs are high impedance when in power-down mode. See the detailed per pin description for the behavior of each device I/O signal during pin-based and register-based power down.

High Speed CML Output

The high-speed data output driver is implemented using Current Mode Logic (CML) with integrated pullup resistors, requiring no external components. The transmit outputs must be AC-coupled.

TLK10002 hi_speed_io_llse75.gif Figure 20. Example of High-Speed I/O AC-Coupled Mode (Channel A HS Side is Shown)

Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK10002 has on-chip 50-Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements. The transmitter output driver is highly configurable allowing output amplitude and de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for very flexible output amplitude control. Only AC-coupled output mode is supported.

When transmitting data across long lengths of PCB trace or cable, the high-frequency content of the signal is attenuated due to the skin effect of the media. This causes a smearing of the data eye when viewed on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide equalization for the high frequency loss, 3-tap finite impulse response (FIR) transmit de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output swing is controlled via MDIO.

Figure 2 illustrates the output waveform flexibility. The level of de-emphasis is programmable through the MDIO interface through control registers (5.7:4 and 5.12:8) through pre-cursor and post-cursor settings. Users can control the strength of the de-emphasis to optimize for a specific system requirement.

High Speed Receiver

The high-speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly tied to 0.8 × VDDT with a capacitor to create an AC ground.

TLK10002 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be enabled or disabled through register settings. Both the gain and bandwidth of the equalizer are controlled by the receiver equalization logic.

Loss of Signal Indication (LOS)

Loss of input signal detection is based on the voltage level of each serial input signal INA x P/N, INB x P/N, HSRXAP/N, and HSRXBP/N. When LOS indication is enabled and a channel's differential serial receive input level is < 75 mVpp, that channel's respective LOS indicator (LOSA or LOSB) is asserted (high true). If the input signal is >150 mVpp, the LOS indicator is deasserted (low false). Outside of these ranges, the LOS indication is undefined. The LOS indicators are also directly readable through the MDIO interface.

The following additional critical status conditions can be combined with the loss of signal condition enabling additional real-time status signal visibility on the LOSA and LOSB outputs per channel:

  1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated LOS condition (per channel).
  2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
  3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
  4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
  5. AZDONE (Auto Zero Calibration Done) – Inverted and Logically OR’d with LOS conditions(s) when enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).

Figure 21 shows the detailed implementation of the LOSA signal along with the associated MDIO control registers.

TLK10002 LOSA_cir_llse75.gif

NOTE:

LOSA is asserted (driven high) during a failing condition, and deasserted (driven low) otherwise. Any combinations of status signals may be enabled onto LOSA/B on MDIO register bits indicated above. LOSB circuit is similar.
Figure 21. LOSA – Logic Circuit Implementation

MDIO Management Interface

The TLK10002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.

The MDIO Interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The port address is determined by control pins PRTAD[4:0] as described in Pin Configuration and Functions.

In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2 individual channels in TLK10002 are classified as 2 different ports. So for any PRTAD[4:1] value there are 2 ports per TLK10002.

TLK10002 responds if the 4 MSB’s of PHY address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) determines which channel/port within TLK10002 to respond to.

If PA[0] = 1'b0, TLK10002 Channel A will respond.

If PA[0] = 1'b1, TLK10002 Channel B responds.

Write transactions which address an invalid register or device, or a read-only register, are ignored. Read transactions which address an invalid register return a 0.

MDIO Protocol Timing

The Clause 22 timing required to read from the internal registers is shown in Figure 22. The Clause 22 timing required to write to the internal registers is shown in Figure 23.

TLK10002 timing1_llse75.gif
Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK10002.
Figure 22. CL22 - Management Interface Read Timing1
TLK10002 timing2_llse75.gif Figure 23. CL22 - Management Interface Write Timing

Clause 22 Indirect Addressing

The TLK10002 Register space is divided into two register groups. One register group can be addressed directly through Clause 22, and one register group can be addressed indirectly through Clause 22. The register group which can be addressed through Clause 22 indirectly is implemented in the vendor specific register space (16’h8000 onwards). Due to Clause 22 register space limitations, an indirect addressing method is implemented so that this extended register space can be accessed through Clause 22. To access this register space (16’h8000 onwards), an address control register (Reg 30, 5’h1E) must be written with the register address followed by a read or write transaction to address data register (Reg 31, 5’h1F) to access the contents of the address specified in address control register.

Figure 24 and Figure 25 illustrate an example write transaction to Register 16’h8000 using indirect addressing in Clause 22.

TLK10002 timing3_llse75.gif Figure 24. CL22 – Indirect Address Method – Address Write
TLK10002 timing4_llse75.gif Figure 25. CL22 - Indirect Address Method – Data Write

Figure 26 and Figure 27 illustrate an example read transaction to read contents of Register 16’h8000 using indirect addressing in Clause 22.

TLK10002 timing5_llse75.gif Figure 26. CL22 - Indirect Address Method – Address Write
TLK10002 timing6_llse75.gif
Note that the 1 in the Turn Around section is externally pulled up, and driven to Zero by TLK10002.
Figure 27. CL22 - Indirect Address Method – Data Read1

The IEEE 802.3 Clause 22 specification defines many of the registers, and additional registers have been implemented for expanded functionality.

Device Functional Modes

Transmit (Low Speed to High Speed) Data Path

The TLK10002 transmit data path with the device configured to operate in the normal transceiver (mission) mode is as shown in Figure 28 and Figure 29. In this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is received by the low-speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32-bits of lane aligned parallel data is subsequently fed into a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B encoded parallel data is handed to the high-speed side SERDES for serialization and output through the HSTX*P/N pins. This process is exactly the same for both Channel A and Channel B.

TLK10002 TX_dataA_llse75.gif Figure 28. Transmit Data Path for the 2:1 Mode
TLK10002 TX_data_llse75.gif Figure 29. Transmit Data Path for the 4:1 Mode

Receive (High Speed to Low Speed) Data Path

With the device configured to operate in the normal transceiver (mission) mode, the receive data path is as shown in Figure 31. 8B/10B encoded serial data (HSRX*P/N) is received by the high-speed side SERDES and deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is fed into the low-speed side SERDES for serialization and output through the OUT*P/N pins. This process is exactly the same for both Channel A and Channel B.

TLK10002 RX_dataA_llse75.gif Figure 30. Receive Data Path for the 2:1 Modes
TLK10002 RX_data_llse75.gif Figure 31. Receive Data Path for the 4:1 Modes

1:1 Retime Mode

In the 1:1 Retime mode shown in Figure 32, the lane alignment and 8B/10B encoding/decoding blocks are not included in the data path. In the transmit data path, low-speed side data received on the IN*0P/N pins is deserialized, phase corrected by the transmit FIFO, and serialized again before it is output through the HSTX*P/N pins. In the receive data path, high-speed side data received on the HSRX*P/N pins is deserialized, phase corrected by the receive FIFO, and serialized again before it is output through the OUT*0P/N pins. All SERDES controls such as preemphasis, swing, equalizer in registers HS/LS_SERDES_CONTROL_*, and loopback modes are supported as in the 2:1 and 4:1 modes.

TLK10002 mode_tx_rx_llse75.gif Figure 32. 1:1 Mode Transmit and Receive Data Paths

The 1:1 mode only uses lane 0 on the low-speed side and is enabled by setting TX_MODE_SEL and RX_MODE_SEL to 1 (1.13:12 = 2'b11) per channel. The maximum data rate supported in the 1:1 mode is 5Gbps. The minimum data rate supported is 1Gbps. LS_OK_OUT_* status pin must be ignored. If needed for monitoring the link status, only PLL lock and LOS are relevant.

The latency measurement function is not supported in the 1:1 mode. In the 1:1 mode, the High-Speed Channel Sync (register F.10) and Low-Speed Lane 0 Channel Sync (register 15.8) are not part of their respective data paths.

In the 1:1 mode, the data path supports non-8B/10B encoded data, for example, PRBS.

In this mode, any registers related to lane 1, 2, or 3 are not used or do not apply. In addition, the following registers do not apply:

  • 1.11:8
  • 9.8:4
  • C, D, 15(except 15.10), 16, 17, 18, 1D
  • F.14, F.10, F.8, F.3:2

Programming

Registers for the TLK10002 can be addressed directly through MDIO Clause 22. Channel identification is based on PHY (Port) address field. Channel A can be accessed by setting LSB of PHY address to 0. Channel B can be accessed by setting LSB of PHY address to 1. Control registers 0x01 through 0x0E are specific to the channel addressed. Status registers 0x0F through 0x15, and 0x1D report the status of the channel addressed. The rest are global control or status registers and are channel independent.

NOTE

The N.x:y register numbering format is used in this document, where N is a hexadecimal register number, and x:y is a register bit number range in decimal format. For example, B.10:8 denotes bits 10, 9, and 8 of register address 0x0B.

Power Sequencing Guidelines

The TLK10002 allows either the core or I/O power supply to be powered up for an indefinite period of time while the other supply is not powered up, if all of the following conditions are met:

  1. All maximum ratings and recommended operating conditions are followed.
  2. Bus contention while 1.5-V or 1.8-V power is applied (> 0 V) must be limited to 100 hours over the projected lifetime of the device.
  3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute maximum voltage values for up to 100 hours of lifetime operation at a junction temperature of 105°C or lower will minimally impact reliability.

The TLK10002 inputs are not failsafe (that is, cannot be driven with the I/O power disabled). TLK10002 inputs must not be driven high until their associated power supplies are active.

Register Maps

    RW: Read-Write User can write 0 or 1 to this register bit. Reading this register bit returns the same value that has been written.
    RW/SC: Read-Write Self-Clearing User can write 0 or 1 to this register bit. Writing a 1 to this register creates a high pulse. Reading this register bit always returns 0.
    RO: Read-Only This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value.
    RO/LH: Read-Only Latched High This register can only be read. Writing to this register bit has no effect. Reading a 1 from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a 0 from this register bit indicates that the condition is not occurring presently, and it has not occurred since the last time the register was read. A latched high register, when read high, must be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read will read low. If it is still occurring, the second read reads high. Reading this register bit automatically resets its value to 0.
    RO/LL: Read-Only Latched Low This register can only be read. Writing to this register bit has no effect. Reading a 0 from this register bit indicates that either the condition is occurring or it has occurred since the last time it was read. Reading a 1 from this register bit indicates that the condition is not occurring presently, and it has not occurred because the last time the register was read. A latched low register, when read low, should be read again to distinguish if a condition occurred previously or is still occurring. If it occurred previously, the second read reads high. If it is still occurring, the second read reads low. Reading this register bit automatically sets its value to 1.
    COR: Clear-On-Read This register can only be read. Writing to this register bit has no effect. Reading from this register bit returns its current value, then resets its value to 0.

Table 9. GLOBAL_CONTROL_1 — Address: 0x00 Default: 0x0600

BIT(s) NAME DESCRIPTION ACCESS
0.15 GLOBAL_RESET Global reset (Channel A & B). RW
SC(1)
0 =
1 =
Normal operation (Default 1’b0)
Resets TX and RX datapath including MDIO registers. Equivalent to asserting RESET_N.
0.11 GLOBAL_WRITE Global write enable. RW
0 = Control settings written to Registers 0x01-0x0E are specific to channel addressed (Default 1’b0)
1 = Control settings written to Registers 0x01-0x0E are applied to both Channel A and Channel B regardless of channel addressed
0.10:8 RESERVED For TI use only (Default 3’b110) RW
0.7 RESERVED For TI use only (Default 1’b0) RW
0.3:0 PRBS_PASS_OVERLAY [3:0] PRBS_PASS pin status selection. Applicable only when PRBS test pattern verification is enabled on HS side or LS side. PRBS_PASS pin reflects PRBS verification status on selected Channel HS/LS side R/W
0000 =
0001 =
001x =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
101x =
1100 =
1101 =
1110 =
1111 =
Status from Channel A HS SERDES side(Default 4’b0000)
Reserved
Reserved
Status from Channel A LS SERDES side Lane 0
Status from Channel A LS SERDES side Lane 1
Status from Channel A LS SERDES side Lane 2
Status from Channel A LS SERDES side Lane 3
Status from Channel B HS SERDES side
Reserved
Reserved
Status from Channel B LS SERDES side Lane 0
Status from Channel B LS SERDES side Lane 1
Status from Channel B LS SERDES side Lane 2
Status from Channel B LS SERDES side Lane 3
After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

Table 10. CHANNEL_CONTROL_1 — Address: 0x01 Default: 0x0300

BIT(s) NAME DESCRIPTION ACCESS
1.15 POWERDOWN Setting this bit high powers down entire data path with the exception that MDIO interface stays active. RW
0 =
1 =
Normal operation (Default 1’b0)
Power Down mode is enabled.
1.13 RX_MODE_SEL RX mode selection RW
0 =
1 =
RX mode dependent upon RX_DEMUX_SEL (1.9) (Default 1’b0)
Enables 1 to 1 mode on receive channel
1. 12 TX_MODE_SEL TX mode selection RW
0 =
1 =
TX mode dependent upon TX_DEMUX_SEL (1.8) (Default 1’b0)
Enables 1 to 1 mode on transmit channel
1.11:10 HS_CH_SYNC_
HYSTERESIS[1:0]
Channel synchronization hysteresis control on the HS receive channel. RW
00 = The channel synchronization, when in the synchronization state, performs the Ethernet standard specified hysteresis to return to the unsynchronized state (Default 2’b00)
01 = A single 8b/10b invalid decode error or disparity error causes the channel synchronization state machine to immediately transition from sync to unsync
10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the channel synchronization state machine to immediately transition from sync to unsync
11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the channel synchronization state machine to immediately transition from sync to unsync
1.9 RX_DEMUX_SEL RX De-Mux selection control for lane de-serialization on receive channel. Valid only when RX_MODE_SEL (1.13) is LOW RW
0 =
1 =
1 to 2
1 to 4 (Default 1’b1)
1. 8 TX_MUX_SEL TX Mux selection control for lane serialization on transmit channel. Valid only when TX_MODE_SEL (1.12) is LOW RW
0 =
1 =
2 to 1
4 to 1 (Default 1’b1)
1.7:4 CLKOUT_DIV[3:0] Output clock divide setting. This value is used to divide selected clock (Selected using CLKOUT_SEL (1.3:2)) before giving it out onto CLKOUTxP/N. RW
0000 =
0001 =
0010 =
0011 =
0100 =
0101 =
0110 =
0111 =
1000 =
1001 =
1010 =
1011 =
1100 =
1101 =
1110 =
1111 =
Divide by 1 (Default 4’b0000)
RESERVED
RESERVED
RESERVED
Divide by 2
RESERVED
RESERVED
RESERVED
Divide by 4
Divide by 8
Divide by 16
RESERVED
Divide by 5
Divide by 10
Divide by 20
Divide by 25
See Figure 13. Clocking Architecture
1.3:2 CLKOUT_SEL[1:0] Output clock select. Selected Recovered clock sent out on CLKOUTxP/N pins RW
00 = Selects Channel A HSRX recovered byte clock as output clock (Default 2’b00)
01 = Selects Channel B HSRX recovered byte clock as output clock
10 = Selects Channel A HSRX VCO divide by 2 clock as output clock
11 = Selects Channel B HSRX VCO divide by 2 clock as output clock
See Figure 13. Clocking Architecture
1.1 REFCLK_ SEL Channel Reference clock selection. Applicable only when REFCLKx_SEL pin is LOW. RW
0 =
1 =
Selects REFCLK_0_P/N as clock reference to Channel x (Default 1’b0)
Selects REFCLK_1_P/N as clock reference to Channel x
See Figure 13. Clocking Architecture
1.0 RESERVED For TI use only (Default 1’b0) RW

Table 11. HS_SERDES_CONTROL_1 — Address: 0x02 Default: 0x811D

BIT(s) NAME DESCRIPTION ACCESS
2.15:10 RESERVED For TI use only (Default 6'b100000) RW
2.9:8 HS_LOOP_BANDWIDTH[1:0] HS SERDES PLL Loop Bandwidth settings RW
00 =
01 =
10 =
11 =
Reserved
Applicable when external JC_PLL is NOT used (Default 2’b01)
Applicable when external JC_PLL is used
Reserved
2.7 RESERVED For TI use only (Default 1’b0) RW
2.6 HS_VRANGE HS SERDES PLL VCO range selection. This bit needs to be set HIGH if VCO frequency (REFCLK * HS_PLL_MULT) is below 2.5GHz RW
0 =
1 =
VCO runs at higher end of frequency range (Default 1’b0)
VCO runs at lower end of frequency range
2.5 RESERVED For TI use only (Default 1’b0) RW
2.4 HS_ENPLL HS SERDES PLL enable control. HS SERDES PLL is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. RW
0 =
1 =
Disables PLL in HS SERDES
Enables PLL in HS SERDES (Default 1’b1)
2.3:0 HS_PLL_MULT[3:0] HS SERDES PLL multiplier setting (Default 4’b1101). Refer to Table 12 RW
See Line Rate, SERDES PLL Settings, and Reference Clock Selection for more information on PLL multiplier settings

Table 12. High-Speed Side SERDES PLL Multiplier Control

2.3:0 2.3:0
VALUE PLL MULTIPLIER FACTOR VALUE PLL MULTIPLIER FACTOR
0000 Reserved 1000 12x
0001 Reserved 1001 12.5x
0010 4x 1010 15x
0011 5x 1011 16x
0100 6x 1100 16.5x
0101 8x 1101 20x
0110 8.25x 1110 25x
0111 10x 1111 Reserved

Table 13. HS_ SERDES_CONTROL_2 — Address: 0x03 Default: 0xA444

BIT(s) NAME DESCRIPTION ACCESS
3.15:12 HS_SWING[3:0] Transmitter Output swing control for HS SERDES. (Default 4’b1010) Refer to Table 14 RW
3.11 RESERVED For TI use only (Default 1’b0) RW
3.10 HS_ENTX HS SERDES transmitter enable control. HS SERDES transmitter is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. RW
0 =
1 =
Disables HS SERDES transmitter
Enables HS SERDES transmitter (Default 1’b1)
3.9:8 HS_RATE_TX [1:0] HS SERDES TX rate settings RW
00 =
01 =
10 =
11 =
Full rate (Default 2’b00)
Half rate
Quarter rate
Eighth rate
3.7:6 HS_AGCCTRL[1:0] Adaptive gain control loop RW
00 = Attenuator will not change after lock has been achieved, even if AGC becomes unlocked
01 = Attenuator will not change when in lock state, but could change when AGC becomes unlocked (Default 2’b01)
10 = Force the attenuator off.
11 = Force the attenuator on
3.5:4 HS_AZCAL[1:0] Auto zero calibration. RW
00 =
01 =
10 =
11 =
Auto zero calibration initiated when receiver is enabled (Default 2’b00)
Auto zero calibration disabled
Forced with automatic update.
Forced without automatic update
3.3 HS_ENUNSD 0 = Disable use of unscrambled data in HS Serdes Rx (Recommended setting for Full Rate) (Default 1’b0) RW
1 = Enable use of unscrambled data in HS Serdes Rx (Recommended setting for Half, Quarter and Eighth Rates)
3.2 HS_ENRX HS SERDES receiver enable control. HS SERDES receiver is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. RW
0 =
1 =
Disables HS SERDES receiver
Enables HS SERDES receiver (Default 1’b1)
3.1:0 HS_RATE_RX [1:0] HS SERDES RX rate settings RW
00 =
01 =
10 =
11 =
Full rate (Default 2’b00)
Half rate
Quarter rate
Eighth rate

Table 14. High-Speed Side SERDES AC Mode Output Swing Control

VALUE
[15:12]
AC MODE
TYPICAL AMPLITUDE (mVdfpp)
0000 130
0001 220
0010 300
0011 390
0100 480
0101 570
0110 660
0111 750
1000 830
1001 930
1010 1020
1011 1110
1100 1180
1101 1270
1110 1340
1111 1400

Table 15. HS_ SERDES_CONTROL_3 — Address: 0x04 Default: 0xB820

BIT(s) NAME DESCRIPTION ACCESS
4.15 HS_ENTRACK HSRX ADC Track mode RW
0 =
1 =
Normal operation
Forces ADC into track mode (Default 1’b1)
4.14:12 HS_EQPRE[2:0] SERDES Rx precursor equalizer selection RW
000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =
1/9 cursor amplitude
3/9 cursor amplitude
5/9 cursor amplitude
7/9 cursor amplitude (Default 3’b011)
9/9 cursor amplitude
11/9 cursor amplitude
13/9 cursor amplitude
Disable
4.11:10 HS_CDRFMULT[1:0] Clock data recovery algorithm frequency multiplication selection RW
00 =
01 =
10 =
11 =
First order. Frequency offset tracking disabled
Second order. 1x mode
Second order. 2x mode (Default 2’b10)
Reserved
4.9:8 HS_CDRTHR[1:0] Clock data recovery algorithm threshold selection RW
00 =
01 =
10 =
11 =
Four vote threshold (Default 2’b00)
Eight vote threshold
Sixteen vote threshold
Thirty two vote threshold
4.7 HS_EQLIM HSRX Equalizer limit control RW
0 =
1 =
Normal operation (Default 1’b0)
Limits equalizer DFE tap weights
4.6 HS_EQHLD HSRX Equalizer hold control RW
0 =
1 =
Normal operation (Default 1’b0)
Holds equalizer and long tail correction in their current state
4.5 HS_H1CDRMODE 0 = CDR locks to h(-1) RW
1 = CDR locks to h(+1)
4.4:0 HS_TWCRF[4:0] Cursor Reduction Factor (Default 5’b00000) Refer to Table 16 RW

Table 16. High-Speed Side SERDES Cursor Reduction Factor Weights

4.4:0 4.4:0
VALUE CURSOR REDUCTION (%) VALUE CURSOR REDUCTION (%)
00000 0 10000 17
00001 2.5 10001 20
00010 5.0 10010 22
00011 7.5 10011 25
00100 10.0 10100 27
00101 12 10101 30
00110 15 10110 32
00111 Reserved 10111 35
01000 11000 37
01001 11001 40
01010 11010 42
01011 11011 45
01100 11100 47
01101 11101 50
01110 11110 52
01111 11111 55

Table 17. HS_ SERDES_CONTROL_4— Address: 0x05 Default: 0x2000

BIT(s) NAME DESCRIPTION ACCESS
5.15 HS_RX_INVPAIR Receiver polarity. RW
0 = Normal polarity. HSRXxP considered positive data. HSRXxN considered negative data (Default 1’b0)
1 = Inverted polarity. HSRXxP considered negative data. HSRXxN considered positive data
5.14 HS_TX_INVPAIR Transmitter polarity. RW
0 = Normal polarity. HSTXxP considered positive data and HSTXxN considered negative data (Default 1’b0)
1 = Inverted polarity. HSTXxP considered negative data and HSTXxN considered positive data
5.13 HS_FIRUPT HS SERDES Tx pre/post cursor filter update control RW
0 = Holds last state; any changes to TWCRF, TWPRE, TWPOST1/2 will not take effect until FIRUPT goes high.
1 = Pre/Post cursor fields can be updated by changing respective fields (Default 1’b1)
5.12:8 HS_TWPOST1[4:0] Adjacent post cursor1 Tap weight. Selects TAP settings for TX waveform. (Default 5’b00000)
Refer to Table 18
RW
5.7:4 HS_TWPRE[3:0] Precursor Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000)
Refer to Table 20
RW
5.3:0 HS_TWPOST2[3:0] Adjacent post cursor2 Tap weight. Selects TAP settings for TX waveform. (Default 4’b0000)
Refer to Table 19
RW

Table 18. High-Speed Side SERDES Post-Cursor1 Transmit Tap Weights

5.12:8 5.12:8
VALUE TAP WEIGHT (%) VALUE TAP WEIGHT (%)
00000 0 10000 0
00001 +2.5 10001 –2.5
00010 +5.0 10010 –5.0
00011 +7.5 10011 –7.5
00100 +10.0 10100 –10.0
00101 +12.5 10101 –12.5
00110 +15.0 10110 –15.0
00111 +17.5 10111 –17.5
01000 +20.0 11000 –20.0
01001 +22.5 11001 –22.5
01010 +25.0 11010 –25.0
01011 +27.5 11011 –27.5
01100 +30.0 11100 –30.0
01101 +32.5 11101 –32.5
01110 +35.0 11110 –35.0
01111 +37.5 11111 –37.5

Table 19. High-Speed Side SERDES Post-Cursor2 Transmit Tap Weights

5.3:0 5.3:0
VALUE TAP WEIGHT (%) VALUE TAP WEIGHT (%)
0000 0 1000 0
0001 +2.5 1001 –2.5
0010 +5.0 1010 –5.0
0011 +7.5 1011 –7.5
0100 +10.0 1100 –10.0
0101 +12.5 1101 –12.5
0110 +15.0 1110 –15.0
0111 +17.5 1111 –17.5

Table 20. High-Speed Side SERDES Pre-Cursor Transmit Tap Weights

5.7:4 5.7:4
VALUE TAP WEIGHT (%) VALUE TAP WEIGHT (%)
0000 0 1000 0
0001 +2.5 1001 –2.5
0010 +5.0 1010 –5.0
0011 +7.5 1011 –7.5
0100 +10.0 1100 –10.0
0101 +12.5 1101 –12.5
0110 +15.0 1110 –15.0
0111 +17.5 1111 –17.5

Table 21. LS_ SERDES_CONTROL_1 — Address: 0x06 Default: 0xF115

BIT(s) NAME DESCRIPTION ACCESS
6.15:12 LS_LN_CFG_EN[3:0] Configuration control for LS SERDES Lane settings (Default 4’b1111) RW
[3] corresponds to LN3, [2] corresponds to LN2
[1] corresponds to LN1, [0] corresponds to LN0
0 = Writes to LS_SERDES_CONTROL_2 (register 0x07) and LS_SERDES_CONTROL_3 (register 0x08) control registers do not affect respective LS SERDES lane
1 = Writes to LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 control registers affect respective LS SERDES lane
For example, if subsequent writes to LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 registers need to affect the settings in Lanes 0 and 1, LS_LN_CFG_EN[3:0] should be set to 4’b0011
Read values in LS_SERDES_CONTROL_2 & LS_SERDES_CONTROL_3 reflect the settings value for Lane selected through LS_LN_CFG_EN[3:0].
To read settings for Lane 0, LS_LN_CFG_EN[3:0] should be set to 4’b0001
To read settings for Lane 1, LS_LN_CFG_EN[3:0] should be set to 4’b0010
To read settings for Lane 2, LS_LN_CFG_EN[3:0] should be set to 4’b0100
To read settings for Lane 3, LS_LN_CFG_EN[3:0] should be set to 4’b1000
Read values of LS_SERDES_CONTROL_2 and LS_SERDES_CONTROL_3 registers are not valid for any other LS_LN_CFG_EN[3:0] combination
6.11:10 RESERVED For TI use only(Default 2’b00) RW
6.9:8 LS_LOOP_BANDWIDTH[1:0] LS SERDES PLL Loop Bandwidth settings RW
00 =
01 =
10 =
11 =
Reserved
Applicable when external JC_PLL is NOT used (Default 2’b01)
Applicable when external JC_PLL is used
Reserved
6.7 DEEP_REMOTE_LPBK_CTRL Deep remote loopback control. Works in conjunction with DEEP_REMOTE_LPBK(B:3). Requires setting of LS_TX_ENTEST(8.3) and LS_RX_ENTEST(8.2) for desired lane on the LS side (default 1'b0). RW
00= Deep Remote Loopback Disabled
01= Deep Remote Loopback through pad. The loopback path includes the transmit CML driver and receive sense amps. The link partner connected through INA*P/N or INB*P/N pins must be electrically idle at differential zero with P and N signals at the same voltage.
10= Deep Remote Loopback with CML Driver Disabled. The loopback path is fully digital and excludes the transmit CML driver and receive sense amps. If monitoring OUT* pins is not required, this mode can save power.
11= Deep Remote Loopback with CML Driver Enabled. As above, but the CML driver operates normally.
6.6:5 RESERVED For TI use only (Default 2’b00) RW
6.4 LS_ENPLL LS SERDES PLL enable control. LS SERDES PLL is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. RW
0 =
1 =
Disables PLL in LS SERDES
Enables PLL in LS SERDES (Default 1’b1)
6.3:0 LS_MPY[3:0] LS SERDES PLL multiplier setting (Default 4’b0101). Refer to Table 22
See Line Rate, SERDES PLL Settings, and Reference Clock Selection for more information on PLL multiplier settings
RW

Table 22. Low-Speed Side SERDES PLL Multiplier Control

6.3:0 6.3:0
VALUE PLL MULTIPLIER FACTOR VALUE PLL MULTIPLIER FACTOR
0000 4x 1000 15x
0001 5x 1001 20x
0010 6x 1010 25x
0011 Reserved 1011 Reserved
0100 8x 1100 Reserved
0101 10x 1101 50x
0110 12x 1110 65x
0111 12.5x 1111 Reserved

Table 23. LS_ SERDES_CONTROL_2 — Address: 0x07 Default: 0xDC04

BIT(s) NAME DESCRIPTION ACCESS
7.15 RESERVED For TI use only. (Default 1’b1) RW
7.14:12 LS_SWING[2:0] Output swing control on LS SERDES side. (Default 3’b101)
Refer to Table 24.
RW
7.11 LS_LOS LS SERDES LOS detector control RW
0 =
1 =
Disable Loss of signal detection on LS SERDES lane inputs
Enable Loss of signal detection on LS SERDES lane inputs (Default 1’b1)
7.10 LS_IN_EN LS SERDES input enable control. LS SERDES per input lane is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. Input lanes 3 and 2 are automatically disabled when in 2 to 1 mode RW
0 =
1 =
Disables LS SERDES lane
Enables LS SERDES lane (Default 1’b1)
7.9:8 LS_IN_RATE [1:0] LS SERDES input lane rate settings RW
00 =
01 =
10 =
11 =
Full rate (Default 2’b00)
Half rate
Quarter rate
Reserved
7.7:4 LS_DE[3:0] LS SERDES output de-emphasis settings. (Default 4’b0000) Refer to Table 25 RW
7.3 RESERVED For TI use only . (Default 1’b0) RW
7.2 LS_OUT_EN LS SERDES output lane enable control. LS SERDES per output lane is automatically disabled when PD_TRXx_N is asserted LOW or when register bit 1.15 is set HIGH. Output lanes 3 and 2 are automatically disabled when in 1 to 2 mode. RW
0 =
1 =
Disables LS SERDES lane
Enables LS SERDES lane (Default 1’b1)
7.1:0 LS_OUT_RATE [1:0] LS SERDES output lane rate settings RW
00 =
01 =
10 =
11 =
Full rate (Default 2’b00)
Half rate
Quarter rate
Reserved

Table 24. Low-Speed Side SERDES AC Mode Output Swing Control

VALUE
7.14:12
AC MODE
TYPICAL AMPLITUDE (mVdfpp)
000 190
001 380
010 560
011 710
100 850
101 950
110 1010
111 1050

Table 25. Low-Speed Side SERDES Output De-Emphasis

7.7:4 7.7:4
VALUE AMPLITUDE REDUCTION VALUE AMPLITUDE REDUCTION
(%) dB (%) dB
0000 0 0 1000 38.08 4.16
0001 4.76 0.42 1001 42.85 4.86
0010 9.52 0.87 1010 47.61 5.61
0011 14.28 1.34 1011 52.38 6.44
0100 19.04 1.83 1100 57.14 7.35
0101 23.8 2.36 1101 61.9 8.38
0110 28.56 2.92 1110 66.66 9.54
0111 33.32 3.52 1111 71.42 10.87

Table 26. LS_ SERDES_CONTROL — Address: 0x08 Default: 0x0001

BIT(s) NAME DESCRIPTION ACCESS
8.15 LS_OUT_INVPAIR LS SERDES output lane polarity. (x = Channel A or B, y = Lane 0 or 1 or 2 or 3) RW
0 = Normal polarity. OUTxyP considered positive data. OUTxyN considered negative data (Default 1’b0)
1 = Inverted polarity. OUTxyP considered negative data. OUTxyN considered positive data
8.14 LS_IN_INVPAIR LS SERDES input lane polarity. (x = Channel A or B, y = Lane 0 or 1 or 2 or 3) RW
0 = Normal polarity. INxyP considered positive data and INxyN considered negative data (Default 1’b0)
1 = Inverted polarity. INxyP considered negative data and INxyP considered positive data
8.13:12 RESERVED For TI use only (Default 2’b00) RW
8.11:8 LS_EQ[3:0] LS SERDES Equalization control (Default 4’b0000). Refer to Table 27. RW
8.7 RESERVED For TI use only (Default 1’b0) RW
8.6:4 LS_CDR[2:0] LS SERDES CDR control (Default 3’b000) RW
000 –
001 –
010 –
011 –
100 –
101 –
11x –
1st Order. Threshold of 1
1st Order. Threshold of 17
2nd Order. High precision. Threshold of 1
2nd Order. High precision. Threshold of 17
1st Order. Low precision. Threshold of 1
2nd Order. Low precision. Threshold of 17
Reserved
8.3 LS_TX_ENTEST LS SERDES test mode control on the channel input RW
0 =
1 =
Normal operation (Default 1’b0)
Enable test mode
8.2 LS_RX_ENTEST LS SERDES test mode control on the channel output RW
0 =
1 =
Normal operation (Default 1’b0)
Enable test mode
8.1:0 RESERVED For TI use only (Default 2’b01) RW

Table 27. Low-Speed Side SERDES Equalization

8.11:8 8.11:8
VALUE LOW FREQ GAIN ZERO FREQ VALUE LOW FREQ GAIN ZERO FREQ
0000 Maximum 1000 Adaptive 365 MHz
0001 Adaptive 1001 275 MHz
0010 Reserved 1010 195 MHz
0011 1011 140 MHz
0100 1100 105 MHz
0101 1101 75 MHz
0110 1110 55 MHz
0111 1111 50 MHz

Table 28. HS_OVERLAY_CONTROL — Address: 0x09 Default: 0x0900

BIT(s) NAME DESCRIPTION ACCESS
9.15:10 RESERVED For TI use only. (Default 6’b000010) RW
9.9 HS_PEAK_DISABLE HS Serdes PEAK_DISABLE control RW
0 =
1 =
Track-and-hold has peaking for bandwidth extension
Track-and-hold is without peaking; has flat AC response
9.8 HS_LOS_MASK 0 = HS SERDES LOS status is used to generate HS channel synchronization status. If HS SERDES indicates LOS, channel synchronization indicates synchronization is not achieved RW
1 = HS SERDES LOS status is not used to generate HS channel synchronization status (Default 1’b1)
9.5 HS_CH_SYNC_OVERLAY 0 = LOSx pin does not reflect receive channel loss of channel synchronization status (Default 1’b0) RW
1 = Allows channel loss of synchronization to be reflected on LOSx pin
9.4 HS_INVALID_CODE_OVERLAY 0 = LOSx pin does not reflect receive channel invalid code word error (Default 1’b0) RW
1 = Allows invalid code word error to be reflected on LOSx pin
9.3 HS_AGCLOCK_OVERLAY 0 = LOSx pin does not reflect HS SERDES AGC unlock status (Default 1’b0) RW
1 = Allows HS SERDES AGC unlock status to be reflected on LOSx pin
9.2 HS_AZDONE_OVERLAY 0 = LOSx pin does not reflect HS SERDES auto zero calibration not done status (Default 1’b0) RW
1 = Allows auto zero calibration not done status to be reflected on LOSx pin
9.1 HS_PLL_LOCK_OVERLAY 0 = LOSx pin does not reflect loss of HS SERDES PLL lock status (Default 1’b0) RW
1 = Allows HS SERDES loss of PLL lock status to be reflected on LOSx pin
9.0 HS_LOS_OVERLAY 0 = LOSx pin does not reflect HS SERDES Loss of signal condition (Default 1’b0) RW
1 = Allows HS SERDES Loss of signal condition to be reflected on LOSx pin

Table 29. LS_OVERLAY_CONTROL — Address: 0x0A Default: 0x4000

BIT(s) NAME DESCRIPTION ACCESS
A.15:14 RESERVED For TI use only RW
A.13 BER_TIMER_CLK_EN 0 =
1 =
Disable BER timer clock (Default 1’b0)
Enable BER timer clock
RW
A.12 LS_PLL_LOCK_OVERLAY 0 = LOSx pin does not reflect loss of LS SERDES PLL lock status (Default 1’b0) RW
1 = Allows LS SERDES loss of PLL lock status to be reflected on LOSx pin
A.11:8 LS_CH_SYNC_OVERLAY_LN[3:0] [3] Corresponds to Lane 3, [2] Corresponds to Lane 2 RW
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 = LOSx pin does not reflect LS SERDES lane loss of synchronization condition (Default 1’b0)
1 = Allows LS SERDES lane loss of synchronization condition to be reflected on LOSx pin
A.7:4 LS_INVALID_CODE_OVERLAY_LN[3:0] [3] Corresponds to Lane 3, [2] Corresponds to Lane 2 RW
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 = LOSx pin does not reflect LS SERDES lane invalid code condition (Default 1’b0)
1 = Allows LS SERDES lane invalid code condition to be reflected on LOSx pin
A.3:0 LS_LOS_OVERLAY_LN[3:0 [3] Corresponds to Lane 3, [2] Corresponds to Lane 2 RW
[1] Corresponds to Lane 1, [0] Corresponds to Lane 0
0 = LOSx pin does not reflect LS SERDES lane Loss of signal condition (Default 1’b0)
1 = Allows LS SERDES lane Loss of signal condition to be reflected on LOSx pin

Table 30. LOOPBACK_TP_CONTROL — Address: 0x0B Default: 0x0700

BIT(s) NAME DESCRIPTION ACCESS
B.15:14 RESERVED For TI use only RW
B.13 HS_TP_GEN_EN 0 =
1 =
Normal operation (Default 1’b0)
Activates test pattern generation selected by bits B.10:8
RW
B.12 HS_TP_VERIFY_EN 0 =
1 =
Normal operation (Default 1’b0)
Activates test pattern verification selected by bits B.10:8
RW
B.10:8 HS_TEST_PATT_SEL[2:0] Test Pattern Selection. Note that for CRPAT, TPsync must be high to be valid. See MDIO bit F.15 in Table 34. RW
000 = High Frequency Test Pattern
001 = Low Frequency Test Pattern
010 = Mixed Frequency Test Pattern
011 = CRPAT Short
100 = CRPAT Long
101 = 27 - 1 PRBS pattern
110 = 223 - 1 PRBS pattern
111 = 231 - 1 PRBS pattern (Default 3’b111)
Errors can be checked by reading HS_ERROR_COUNTER register (0x10)
B.7 LS_TP_GEN_EN 0 =
1 =
Normal operation (Default 1’b0)
Activates test pattern generation selected by bits B.5:4 on the LS side
RW
Requires setting of LS_RX_ENTEST (8.2) for desired lane on the LS side
B.6 LS_TP_VERIFY_EN 0 =
1 =
Normal operation (Default 1’b0)
Activates test pattern verification selected by bits B.5:4 on the LS side
Requires setting of LS_TX_ENTEST (8.3) for desired lane on the LS side
RW
B.5:4 LS_TEST_PATT_SEL[1:0] Test Pattern Selection RW
00 =
01 =
10 =
11 =
231 - 1 PRBS pattern (Default 2’b00)
Alternating 0/1 pattern with a period of 2 UI (LS side bit UI)
27 - 1 PRBS pattern
223 - 1 PRBS pattern
B.3 DEEP_REMOTE_LPBK 0 =
1 =
Normal functional mode (Default 1’b0)
Enable deep remote loopback mode
RW
Requires setting of LS_TX_ENTEST(8.3) and LS_RX_ENTEST (8.2) for desired lane on the LS side. See Figure 14 and MDIO bit 6.7 for additional controls.
B.2 SHALLOW_REMOTE_LPBK 0 =
1 =
Normal functional mode (Default 1’b0)
Enable shallow remote loopback mode/serial retime mode
RW
See Figure 15
B.1 DEEP_LOCAL_LPBK 0 =
1 =
Normal functional mode (Default 1’b0)
Enable deep remote loopback mode
RW
See Figure 16
B.0 SHALLOW_LOCAL_LPBK 0 =
1 =
Normal functional mode (Default 1’b0)
Enable shallow local loopback mode
RW
See Figure 17

Table 31. LAS_CONFIG_CONTROL — Address: 0x0C Default: 0x03F0

BIT(s) NAME DESCRIPTION ACCESS
C.15:14 RESERVED For TI use only. (Default 2’b0) RW
C.13:12 LAS_STATUS_CFG[1:0] Selects selected lane status to be reflected in LAS_STATUS_1 register (0x15) RW
00 =
01 =
10 =
11 =
Lane 0 (Default 2’b00)
Lane 1
Lane 2
Lane 3
C.11:10 LAS_CH_SYNC_HYS_SEL[1:0] Lane alignment slave Channel synchronization hysteresis selection RW
00 = The channel synchronization, when in the synchronization state, performs the Ethernet standard specified hysteresis to return to the LOS state (Default 2’b00)
01 = A single 8b/10b invalid decode error or disparity error causes the channel synchronization state machine to immediately transition from sync to LOS
10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the channel synchronization state machine to immediately transition from sync to LOS
11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the channel synchronization state machine to immediately transition from sync to LOS
C.9:8 LAS_LA_COL_CFG[1:0] Minimum distance between align character in Lane alignment slave RW
00 =
01 =
1x =
8
16
24 (Default 2’b11)
C.7 LS_DECODE_ERR_MASK 0 = LS side decode errors of enabled lanes are used to generate link status if error rate exceeds threshold. Valid only when hardware BER function is enabled by setting A.13 to 1'b1. RW
1 = LS side decode errors of any lane are not used to generate link status (Default 1’b1)
C.6 RESERVED For TI use only. RW
C.5 LS_LOS_MASK 0 = LS SERDES LOS status of enabled lanes is used to generate link status RW
1 = LS SERDES LOS status of enabled lanes is not used to generate link status (Default 1’b1)
C.4 LS_PLL_LOCK_MASK 0 = LS SERDES PLL Lock status is used to generate link status RW
1 = LS SERDES PLL Lock status is not used to generate link status (Default 1’b1)
C.2 FORCE_LM_REALIGN 0 = Normal operation (Default 1’b0) RW
SC(1)
1 = Force lane realignment in Link status monitor
C.1:0 LAS_BER_THRESH[1:0] Threshold setting for 8b/10b error rate checking. Valid only when hardware BER function is enabled by setting A.13 to 1'b1. RW
00 = Link Ok if <1 error when timer expires (Default 2’b00)
01 = Link Ok if <15 error when timer expires
10 = Link Ok if <127 error when timer expires
11 = Link Ok if <1023 error when timer expires
After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

Table 32. LAS_BER_TMER_CONTROL — Address: 0x0D Default: 0xFFFF

BIT(s) NAME DESCRIPTION ACCESS
D.15:0 LAS_BER_TIMER[15:0] 16 bit value to configure 8b/10b error rate checking on the link monitor (Default 16’hFFFF). Valid only when hardware BER function is enabled by setting A.13 to 1'b1. RW

Table 33. RESET_CONTROL — Address: 0x0E Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
E.3 DATAPATH_RESET Channel datapath reset control. Required once the desired functional mode is configured. RW
SC(1)
0 =
1 =
Normal operation. (Default 1’b0)
Resets channel logic excluding MDIO registers. (Resets both Tx and Rx datapath)
E.2 TXFIFO_RESET Transmit FIFO reset control RW
SC(1)
0 = Normal operation. (Default 1’b0)
1 = Resets transmit datapath FIFO.
E.1 RXFIFO_RESET Receive FIFO reset control RW
SC(1)
0 = Normal operation. (Default 1’b0)
1 = Resets receive datapath FIFO.
After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.

Table 34. CHANNEL_STATUS_1 — Address: 0x0F Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
F.15 HS_TP_ STATUS Test Pattern status for High/Low/Medium/CRPAT test patterns RO
0 = Alignment has not achieved
1 = Alignment has been determined and correct pattern has been received. Any bit errors are reflected in HS_ERROR_COUNTER register (0x10)
F.14 LA_SLAVE_STATUS Lane alignment slave status
0 = Lane alignment is not achieved on the slave side
1 = Lane alignment is achieved on the slave side
RO/LL
F.13 HS_LOS Loss of Signal Indicator.
When high, indicates that a loss of signal condition is detected on HS serial receive inputs
RO/LH
F.12 HS_AZ_DONE Auto zero complete indicator.
When high, indicates auto zero calibration is complete
RO/LL
F.11 HS_AGC_LOCKED Adaptive gain control loop lock indicator.
When high, indicates AGC loop is in locked state
RO/LL
F.10 HS_CHANNEL_SYNC Channel synchronization status indicator.
When high, indicates channel synchronization has achieved
RO/LL
F.9 RESERVED For TI use only. (Default 1’b0). RO/LH
F.8 HS_DECODE_INVALID Valid when decoder is enabled and during CRPAT test pattern verification.
When high, indicates decoder received an invalid code word, or a 8b/10b disparity error. In functional mode, number of DECODE_INVALID errors are reflected in HS_ERROR_COUNTER register (0x10)
RO/LH
F.7 TX_FIFO_UNDERFLOW When high, indicates underflow has occurred in the transmit datapath FIFO. RO/LH
F.6 TX_FIFO_OVERFLOW When high, indicates overflow has occurred in the transmit datapath FIFO. RO/LH
F.5 RX_FIFO_UNDERFLOW When high, indicates underflow has occurred in the receive datapath FIFO. RO/LH
F.4 RX_FIFO_OVERFLOW When high, indicates overflow has occurred in the receive datapath FIFO. RO/LH
F.3 RX_LS_OK Receive link status indicator from LS side.
When high, indicates receive link status is achieved on the LS side
RO/LL
F.2 TX_LS_OK Link status indicator from Link training slave inside TLK10002
When high, indicates Link training slave has achieved sync and alignment
RO/LL
F.1 LS_PLL_LOCK LS SERDES PLL lock indicator
When high, indicates LS SERDES PLL is locked to the selected incoming REFCLK0/1_P/N
RO/LL
F.0 HS_PLL_LOCK HS SERDES PLL lock indicator
When high, indicates HS SERDES PLL is locked to the selected incoming REFCLK0/1_P/N
RO/LL

Table 35. HS_ERROR_COUNTER — Address: 0x10 Default: 0xFFFD

BIT(s) NAME DESCRIPTION ACCESS
10.15:0 HS_ERR_COUNT [15:0] In functional mode, this counter reflects number of invalid code words (including disparity errors) received by decoder.
In HS test pattern verification mode, this counter reflects error count for the test pattern selected through B.10:8
When PRBSEN pin is set, this counter reflects error count for selected PRBS pattern. Counter value cleared to 16’h0000 when read.
COR

Table 36. LS_LN0_ERROR_COUNTER — Address: 0x11 Default: 0xFFFD

BIT(s) NAME DESCRIPTION ACCESS
11.15:0 LS_LN0_ERR_COUNT [15:0] Lane 0 Error counter
In functional mode, this counter reflects number of invalid code words (including disparity errors) received by decoder in lane alignment slave.
In LS test pattern verification mode, this counter reflects error count for the test pattern selected through B.5:4
Counter value cleared to 16’h0000 when read.
COR

Table 37. LS_LN1_ERROR_COUNTER — Address: 0x12 Default: 0xFFFD

BIT(s) NAME DESCRIPTION ACCESS
12.15:0 LS_LN1_ERR_COUNT [15:0] Lane 1 Error counter
In functional mode, this counter reflects number of invalid code words (including disparity errors) received by decoder in lane alignment slave.
In LS test pattern verification mode, this counter reflects error count for the test pattern selected through B.5:4
Counter value cleared to 16’h0000 when read.
COR

Table 38. LS_LN2_ERROR_COUNTER — Address: 0x13 Default: 0xFFFD

BIT(s) NAME DESCRIPTION ACCESS
13.15:0 LS_LN2_ERR_COUNT [15:0] Lane 2 Error counter
In functional mode, this counter reflects number of invalid code words (including disparity errors) received by decoder in lane alignment slave.
In LS test pattern verification mode, this counter reflects error count for the test pattern selected through B.5:4
Counter value cleared to 16’h0000 when read.
COR

Table 39. LS_LN3_ERROR_COUNTER — Address: 0x14 Default: 0xFFFD

BIT(s) NAME DESCRIPTION ACCESS
14.15:0 LS_LN3_ERR_COUNT [15:0] Lane 3 Error counter
In functional mode, this counter reflects number of invalid code words (including disparity errors) received by decoder in lane alignment slave.
In LS test pattern verification mode, this counter reflects error count for the test pattern selected through B.5:4
Counter value cleared to 16’h0000 when read.
COR

Table 40. LAS_STATUS_1 — Address: 0x15 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
15.15 LAS_LN_ALIGN_FIFO_ERR LAS Lane alignment FIFO error status RO/LH
0 = FIFO error not detected
1 = FIFO error detected
15.14:12 RESERVED For TI use only RO
15.11 LAM_ ALIGN_SEQ_ST LAM Lane align sequence state
0 = Sending normal traffic
1 = Sending lane align sequence
RO
15.10 LS_LOS Loss of Signal Indicator.
When high, indicates that a loss of signal condition is detected on LS serial receive inputs for selected lane. Lane can be selected through LAS_STATUS_CFG[1:0] (register C.13:12)
RO/LH
15.9 RESERVED For TI use only. (Default 1’b0). RO/LL
15.8 LAS_CH_SYNC_STATUS LAS Channel sync status for selected lane. Lane can be selected through LAS_STATUS_CFG[1:0] (register C.13:12) RO/LL
15.6:4 RESERVED For TI use only. (Default 2’b000). RO
15.3 LAS_INVALID_DECODE LAS Invalid decode error for selected lane. Lane can be selected through LAS_STATUS_CFG[1:0] (register C.13:12). Error count for each lane can also be monitored through respective LS_LNx_ERROR_COUNTER registers (0x11, 0x12, 0x13, and 0x14) RO/LH
15.2:0 RESERVED For TI use only. (Default 2’b000). RO

Table 41. LATENCY_MEASURE_CONTROL — Address: 0x16 Default: 0x7F00

BIT(s) NAME DESCRIPTION ACCESS
16.15:8 RESERVED For TI use only (Default 8'b11111111) RW
16.7 LATENCY_MEAS_START_SEL Latency measurement start point selection RW
0 = Selects LS TX as start point (Default 1’b0)
1 = Selects HS RX as start point
16.6 LATENCY_MEAS_STOP_SEL Latency measurement stop point selection RW
0 = Selects LS RX as stop point (Default 1’b0)
1 = Selects HS TX as stop point
16.5:4 LATENCY_MEAS_CLK_DIV[1:0] Latency measurement clock divide control. Valid only when bit 16.2 is 0. Divides clock to needed resolution. Higher the divide value, lesser the latency measurement resolution. In choosing a divider, note that the frequency of the divided clock should not be slower than the internal high speed byte clock. RW
00 = Divide by 1 (Default 2’b00) (Most Accurate Measurement)
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8 (Longest Measurement Capability)
See Table 8
16.2 LATENCY_MEAS_CLK_SEL Latency measurement clock selection. RW
0 = Selects clock listed in Table 8. Bits 16.5:4 can be used to divide this clock to achieve needed resolution. (Default 1’b0)
1 = Selects respective channel recovered byte clock (Frequency = Serial bit rate/ 20).
16.1 LATENCY_MEAS_EN Latency measurement enable RW
0 = Disable Latency measurement (Default 1’b0)
1 = Enable Latency measurement
16.0 LATENCY_MEAS_CH_SEL Latency measurement channel selection RW
0 = Selects Latency measurement for channel A (Default 1’b0)
1 = Selects Latency measurement for channel B

Table 42. LATENCY_COUNTER_2 — Address: 0x17 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
17.15:12 LATENCY_MEAS_START_COMMA[3:0] Latency measurement start comma location status. 1 indicates comma found at the start location. If LS TX is selected as start point (16.7 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS RX is selected as start point (16.7 = 1), [0] indicates status for data[9:0], [1] indicates status for data[19:10]. [3:2] is unused. RO/LH(1)
17.11:8 LATENCY_MEAS_STOP_COMMA[3:0] Latency measurement stop comma location status. 1 indicates comma found at the stop location. If LS RX is selected as stop point (16.6 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS TX is selected as stop point (16.6 = 1), [0] indicates status for data[9:0], [1] indicates status for data[19:10]. [3:2] is unused. RO/LH(1)
17.4 LATENCY_ MEAS_READY Latency measurement ready indicator RO/LH(1)
0 = Indicates latency measurement not complete.
1 = Indicates latency measurement is complete and value in latency measurement counter (LATENCY_MEAS_COUNT[19:0]) (in registers 17.3:0 and 18.15:0) is ready to be read.
17.3:0 LATENCY_MEAS_COUNT[19:16] Bits[19:16] of 20 bit wide latency measurement counter. COR(1)
Latency measurement counter value represents the latency in number of clock cycles. This counter will return 20’h00000 if it is read before a comma is received at the stop point. If latency is more than 20’hFFFFF clock cycles then this counter returns 20’hFFFFF.
User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to 20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when Register 0x18 is read.

Table 43. LATENCY_COUNTER_1 — Address: 0x18 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
18.15:0 LATENCY_MEAS_COUNT[15:0] Bits[15:0] of 20-bit wide latency measurement counter. COR(1)
User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to 20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when Register 0x18 is read.

Table 44. TI_RESERVED_CONTROL_1 — Address: 0x19 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
19.10 RESERVED For TI use only. (Default 1’b0) RW
19.9 RESERVED For TI use only. (Default 1’b0) RW
19.8 RESERVED For TI use only. (Default 1’b0) RW
19.6 RESERVED For TI use only. (Default 1’b0) RW
19.5:4 RESERVED For TI use only. (Default 2’b00) RW
19.3:0 RESERVED For TI use only. (Default 4’b0000) RW

Table 45. TI_RESERVED_CONTROL_2 — Address: 0x1A Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
1A.15:0 RESERVED For TI use only. RW

Table 46. TI_RESERVED_STATUS_1 — Address: 0x1B Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
1B.15:0 RESERVED For TI use only. RO

Table 47. MISC_CONTROL_3 — Address: 0x1C Default: 0x3000

BIT(s) NAME DESCRIPTION ACCESS
1C.15 RESERVED For TI use only. (Default 1’b0) RW
1C.14 RESERVED For TI use only. (Default 1’b0) RW
1C.13 CLKOUT_B_EN Output clock enable RW
0 = Holds CLKOUTBP/N output to a fixed value
1 = Allows CLKOUTBP/N output to toggle normally (Default 1'b1)
1C.12 CLKOUT_A_EN Output clock enable RW
0 = Holds CLKOUTAP/N output to a fixed value
1 = Allows CLKOUTAP/N output to toggle normally (Default 1'b1)
1C.9:0 RESERVED For TI use only. (Default 10’b0000000000) RW

Table 48. LAS_STATUS_2 — Address: 0x1D Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
1D.15:12 LAS_LN3_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 3. RO
1D.11:8 LAS_LN2_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 2. RO
1D.7:4 LAS_LN1_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 1. RO
1D.3:0 LAS_LN0_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 0. RO

Table 49. EXT_ADDRESS_CONTROL — Address: 0x1E Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
1E.15:0 EXT_ADDR_CONTROL[15:0] This register must be written with the extended register address to be written/read. Contents of address written in this register can be accessed from Register 0x1F. (Default 4’h0000) RW

Table 50. EXT_ADDRESS_DATA — Address: 0x1F Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
1F.15:0 EXT_ADDR_DATA[15:0] This register contains the data associated with the register address written in Register 0x1E RO

Table 51. TI_ RESERVED_STATUS_2 — Address: 0x8000 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8000.15:0 RESERVED For TI use only. RO

Table 52. TI_RESERVED_STATUS_3 — Address: 0x8001 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8001.15:0 RESERVED For TI use only. RO

Table 53. TI_RESERVED_STATUS_4 — Address: 0x8002 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8002.15:0 RESERVED For TI use only. RO

Table 54. TI_RESERVED_STATUS_5 — Address: 0x8003 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8003.15:0 RESERVED For TI use only. RO

Table 55. TI_RESERVED_STATUS_6 — Address: 0x8004 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8004.15:0 RESERVED For TI use only. RO

Table 56. TI_RESERVED_STATUS_7 — Address: 0x8005 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8005.15:0 RESERVED For TI use only. RO

Table 57. TI_RESERVED_STATUS_8 — Address: 0x8006 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8006.15:0 RESERVED For TI use only. RO

Table 58. TI_RESERVED_STATUS_9 — Address: 0x8007 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8007.15:0 RESERVED For TI use only. RO

Table 59. TI_RESERVED_STATUS_10 — Address: 0x8008 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8008.15:0 RESERVED For TI use only. RO

Table 60. TI_RESERVED_STATUS_11 — Address: 0x8009 Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
8009.15:0 RESERVED For TI use only. RO

Table 61. TI_RESERVED_STATUS_12 — Address: 0x800A Default: 0x0000

BIT(s) NAME DESCRIPTION ACCESS
800A.15:0 RESERVED For TI use only. RO