ZHCSIG2A July   2018  – August 2018 TLC6C5716-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     典型应用原理图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF-Short and IREF-Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate-Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Grayscale Data Write

The grayscale data is 288 bits long, and contains a 12-bit grayscale value for each output. The grayscale value sets the channel turnon time.Figure 27 shows the GS register configuration. Figure 1 is the GS write timing diagram. Data is latched from the 288-bit common shift register into the GS data latch at the rising edge of the LATCH pin. When data is latched into the GS registers, the new data is immediately available on the constant-current outputs. If the data is latched with BLANK high, the outputs may turn on or off unexpectedly. So users should update the GS data when BLANK is low.

The 12-bit GS function has 4096 brightness steps, from 0% to 99.97% brightness. The GS function is controlled by a 12-bit GS counter. The GS counter increments on each rising edge of the grayscale reference clock GCLK. The falling edge of BLANK resets the GS counter value to 0. The GS counter value stays at 0 while BLANK is low, even if there is a GCLK input. Pulling BLANK high enables the 12-bit GS counter. The first rising edge of a GS clock after BLANK goes high increments the GS counter by one and turns on the outputs. Each additional rising edge increases the GS counter by one. The GS counter monitors the number of clock pulses on the GCLK pin. The output stays on while the counter value is less than or equal to the GS setting value. The output turns off at the rising edge of the GS counter value when the counter is larger than the GS setting value. Table 20 is the on-time duty cycle of each GS data bit when the 12-bit GS counter mode is selected.

When the device is powered up, the 288-bit common shift register and GS data latch are reset to 0.

Equation 4 describes each output on-time.

Equation 4. TLC6C5716-Q1 Turn_On_Time-slasek2.gif

where

  • tGCLK is the GS clock period
  • GS is the programmed grayscale value for each output.

Equation 5 shows the duty-cycle calculation equation.

Equation 5. TLC6C5716-Q1 Duty_Cycle-slasek2.gif
TLC6C5716-Q1 GS-Register-slasek2.gifFigure 27. TLC6C5716-Q1 Grayscale Register

Once the GS data is latched into the GS registers at the rising edge of the LATCH signal, the FC-BC-DC data latch shifts into the lowest 205 bits of the common shift register. So, the FC-BC-DC data can be read out from SDO in GS write. This FC-BC-DC read function can also be realized by the read FC-BC-DC command, see FC-BC-DC Read and Figure 8 for the timing diagram.

Table 19. Grayscale Data Bit Assignments

BITS DATA BITS DATA
287–276 OUTB7 143–132 OUTB3
275–264 Reserved 131–120 Reserved
263–252 OUTR7 119–108 OUTR3
251–240 OUTB6 107–96 OUTB2
239–228 Reserved 95–84 Reserved
227–216 OUTR6 83–72 OUTR2
215–204 OUTB5 71–60 OUTB1
203–192 Reserved 59–48 Reserved
191–180 OUTR5 47–36 OUTR1
179–168 OUTB4 35–24 OUTB0
167–156 Reserved 35–24 Reserved
155–144 OUTR4 11–0 OUTR0

Table 20. GS Data vs Output On Time

GS DATA (BINARY) GS DATA (DECIMAL) GS DATA (HEX) DUTY CYCLE (%) ON-TIME BASED ON 33-MHz GS CLOCK (ns)
0000 0000 0000 0 000 0 0
0000 0000 0001 1 001 0.02 30
0000 0000 0010 2 002 0.05 61
... ... ... ... ...
0111 1111 1111 2047 7FF 49.97 62 030
1000 0000 0000 2048 800 50.00 62 061
1000 0000 0001 2049 801 50.02 62 091
... ... ... ... ...
1111 1111 1101 4093 FFD 99.93 124 030
1111 1111 1110 4094 FFE 99.95 124 061
1111 1111 1111 4095 FFF 99.98 124 091