ZHCSEP3B February   2016  – February 2016 THS3217

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: D2S
    6. 7.6  Electrical Characteristics: OPS
    7. 7.7  Electrical Characteristics: D2S + OPS
    8. 7.8  Electrical Characteristics: Midscale (DC) Reference Buffer
    9. 7.9  Typical Characteristics: D2S + OPS
    10. 7.10 Typical Characteristics: D2S Only
    11. 7.11 Typical Characteristics: OPS only
    12. 7.12 Typical Characteristics: Midscale (DC) Reference Buffer
    13. 7.13 Typical Characteristics: Switching Performance
    14. 7.14 Typical Characteristics: Miscellaneous Performance
  8. Parameter Measurement Information
    1. 8.1 Overview
    2. 8.2 Frequency Response Measurement
    3. 8.3 Harmonic Distortion Measurement
    4. 8.4 Noise Measurement
    5. 8.5 Output Impedance Measurement
    6. 8.6 Step-Response Measurement
    7. 8.7 Feedthrough Measurement
    8. 8.8 Midscale Buffer ROUT Versus CLOAD Measurement
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2-V/V (Pins 2, 3, 6 and 14)
      2. 9.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
      3. 9.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)
        1. 9.3.3.1 Output DC Offset and Drift for the OPS
        2. 9.3.3.2 OPS Harmonic Distortion (HD) Performance
        3. 9.3.3.3 Switch Feedthrough to the OPS
        4. 9.3.3.4 Driving Capacitive Loads
      4. 9.3.4 Digital Control Lines
    4. 9.4 Device Functional Modes
      1. 9.4.1 Full-Signal Path Mode
        1. 9.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
        2. 9.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage
        3. 9.4.1.3 External Connection
      2. 9.4.2 Dual-Output Mode
      3. 9.4.3 Differential I/O Voltage Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Applications
        1. 10.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs
          1. 10.1.1.1.1 Design Requirements
          2. 10.1.1.1.2 Detailed Design Procedure
          3. 10.1.1.1.3 Application Curves
        2. 10.1.1.2 High-Voltage Pulse-Generator
          1. 10.1.1.2.1 Design Requirements
          2. 10.1.1.2.2 Detailed Design Procedure
          3. 10.1.1.2.3 Application Curves
        3. 10.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
          1. 10.1.1.3.1 Design Requirements
        4. 10.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter
          1. 10.1.1.4.1 Design Requirements
        5. 10.1.1.5 Differential I/O Driver With independent Common-Mode Control
          1. 10.1.1.5.1 Design Requirements
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 开发支持
        1. 13.1.1.1 TINA-TI(免费软件下载)
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

The THS3217 typically operates on balanced, split supplies. The specifications and characterization plots use ±6 V in most cases. The full operating range for the THS3217 spans ±4 V to ±7.9 V. The input and output stages have separate supply pins that are isolated internally.

The recommended external supply configuration brings ±VCC into the output stage first, then back to the input stage connections through a π-filter comprised of ferrite beads and added decoupling capacitors at +VCC2 (pin 16) and –VCC2 (pin 5). Figure 106 shows an example decoupling configuration.

THS3217 s12_PwrSup_sbos766.gif Figure 106. Recommended Power-Supply Configuration

The ferrite bead acts to break the feedback loop from the output stage load currents back into the D2S and midscale buffer stages. Operate the two positive supply pins and the two negative supply pins at the same voltage. Using separate sources on the two pins risks forward-biasing the on-chip parallel diodes connecting the two supply inputs together. +VCC1 (pin 13) and +VCC2 (pin 16) have two parallel diodes that are normally off if the voltage at the two pins are equal. The same is true for –VCC1 (pin 8) and –VCC2 (pin 5).

The THS3217 provides considerable flexibility in the supply voltage settings. The overriding consideration is always satisfying the required headroom to the supplies on all the I/O paths. The logic controls on PATHSEL (pin 4) and DISABLE (pin 10) are intended to operate ground referenced regardless of supplies used. The ground connection on pin 7 is used to set the reference.

Power savings are certainly possible by operating with only the minimum required supplies for the intended swings at each of the pins. For instance, consider an example design operating with a current-sinking DAC with the input common-mode voltage at 3 V, with an output swing at the D2S output of ±1 V. Looking at just the D2S stage under these conditions, the minimum positive supply is 3 VCM + the maximum input headroom of 1.5 V to the positive supply, resulting in a minimum 4.5-V supply for this operation. The ±1-V output at VO1 (pin 6) along with the D2S output headroom sets the minimum negative supply voltage. The maximum 1.65-V headroom gives a possible minimum negative supply of –2.65 V. However, the minimum operating total of 8 V increases the negative supply to –3.5 V.

If the ±1-V swing is then amplified by the OPS, the output swing and headroom requirements set the minimum operating supply. For instance, if the OPS is operating at a gain of 2.5 V/V, the ±2.5-V output requires a maximum headroom of 1.4 V to either supply. Achieving a 1.4-V headroom requires a minimum balanced supply of ±3.9 V. However, the input stage overrides the positive side because the required minimum is 4.5 V, while the negative increases to –3.9 V. This example of absolute minimum supplies saves power. Using a typical 56-mA quiescent current for all stages, going to the minimum 8.4 V total across the device, uses 470 mW of quiescent power versus the 672 mW if a simple ±6-V supply is applied. However, ac performance degrades with the lower headroom. For more power-sensitive applications, consider adjusting the supplies to the minimum required on each side.

11.1 Thermal Considerations

The internal power for the THS3217 is a combination of its quiescent power and load power. The quiescent power is simply the total supply voltage times the supply current. This current is trimmed to reduce power dissipation variation and minimize variations in the ac performance. At a ±7.5-V supply, the maximum supply current of 57 mA dissipates 855 mW of quiescent power. The worst-case load power occurs if the output is at ½ the single-sided supply voltage driving a dc load. Placing a ±3.75-V dc output into 100 Ω adds another 37.5 mA × 3.75 V = 140 mW of internal power. This total of approximately 1 W of internal dissipation requires the thermal pad be connected to a good heat-spreading ground plane to hold the internal junction temperatures below the rated maximum of 150°C.

The thermal impedance is approximately 45 °C/W with the thermal pad connected. For 1 W of internal power dissipation there is a 45°C (approximate) rise in the junction temperature from ambient. Designing for the intended 85°C maximum ambient temperature results in a maximum junction temperature of 130°C.