ZHCSJ74A December 2018 – January 2020 TCAN4550
PRODUCTION DATA.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RSVD | |||||||
R | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CEL[7:0] | |||||||
X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RP | REC[6:0] | ||||||
R | R | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEC[7:0] | |||||||
R |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RSVD | R | 0x0 | Reserved |
23:16 | CEL[7:0] | X | 0x0 | CAN Error Logging
The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO |
15 | RP | R | 0 |
0 – The Receive Error Counter is below the error passive level of 128 1 – The Receive Error Counter has reached the error passive level of 128 |
14:8 | REC[6:0] | R | 0x0 | Actual state of the Receive Error Counter, values between 0 and 127 |
7:0 | TEC[7:0] | R | 0x0 | Actual state of the Transmit Error Counter, values between 0 and 255 |
NOTE
When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented.