ZHCSN78E january   2021  – march 2023 TCAN1043A-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings - IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation Ratings
    7. 6.7  Power Supply Characteristics
    8. 6.8  Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Supply Pins
        1. 8.3.1.1 VSUP Pin
        2. 8.3.1.2 VCC Pin
        3. 8.3.1.3 VIO Pin
      2. 8.3.2 Digital Inputs and Outputs
        1. 8.3.2.1 TXD Pin
        2. 8.3.2.2 RXD Pin
        3. 8.3.2.3 nFAULT Pin
        4. 8.3.2.4 EN Pin
        5. 8.3.2.5 nSTB Pin
      3. 8.3.3 GND
      4. 8.3.4 INH Pin
      5. 8.3.5 WAKE Pin
      6. 8.3.6 CAN Bus Pins
      7. 8.3.7 Faults
        1. 8.3.7.1 Internal and External Fault Indicators
          1. 8.3.7.1.1 Power-Up (PWRON Flag)
          2. 8.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 8.3.7.1.3 Undervoltage Faults
            1. 8.3.7.1.3.1 Undervoltage on VSUP
            2. 8.3.7.1.3.2 Undervoltage on VCC
            3. 8.3.7.1.3.3 Undervoltage on VIO
          4. 8.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 8.3.7.1.5 TXD Clamped Low (TXDCLP Flag)
          6. 8.3.7.1.6 TXD Dominant State Timeout (TXDDTO Flag)
          7. 8.3.7.1.7 TXD Shorted to RXD Fault (TXDRXD Flag)
          8. 8.3.7.1.8 CAN Bus Dominant Fault (CANDOM Flag)
      8. 8.3.8 Local Faults
        1. 8.3.8.1 TXD Clamped Low (TXDCLP)
        2. 8.3.8.2 TXD Dominant Timeout (TXD DTO)
        3. 8.3.8.3 Thermal Shutdown (TSD)
        4. 8.3.8.4 Undervoltage Lockout (UVLO)
        5. 8.3.8.5 Unpowered Devices
        6. 8.3.8.6 Floating Terminals
        7. 8.3.8.7 CAN Bus Short-Circuit Current Limiting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Mode Description
        1. 8.4.1.1 Normal Mode
        2. 8.4.1.2 Silent Mode
        3. 8.4.1.3 Standby Mode
        4. 8.4.1.4 Go-To-Sleep Mode
        5. 8.4.1.5 Sleep Mode
          1. 8.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 8.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 8.4.2 CAN Transceiver
        1. 8.4.2.1 CAN Transceiver Operation
          1. 8.4.2.1.1 CAN Transceiver Modes
            1. 8.4.2.1.1.1 CAN Off Mode
            2. 8.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 8.4.2.1.1.3 CAN Active
          2. 8.4.2.1.2 Driver and Receiver Function Tables
          3. 8.4.2.1.3 CAN Bus States
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
      2. 9.1.2 Design Requirements
        1. 9.1.2.1 Bus Loading, Length and Number of Nodes
      3. 9.1.3 Detailed Design Procedure
        1. 9.1.3.1 CAN Termination
    2. 9.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.8 Electrical Characteristics

Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V, VCC = 5 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN Driver Characteristics
VO(D) Dominant output voltage
Bus biasing active		 CANH TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open
See Figure 7-1  and Figure 7-4 		 2.75 4.5 V
CANL 0.5 2.25 V
VO(R) Recessive output voltage
Bus biasing active		 TXD = VIO, RL = open (no load), RCM = open
See Figure 7-1 and  Figure 7-4 		 2 3 V
VSYM Driver symmetry
Bus biasing active
(VO(CANH) + VO(CANL) ) / VCC		 nSTB= VIO, RL = 60 Ω, CSPLIT = 4.7 nF, CL = Open, RCM = Open, TXD = 250 kHz, 1 MHz, 2.5 MHz
See Figure 7-1 and Figure 7-4 		 0.9 1.1 V/V
VSYM_DC DC Driver symmetry
Bus biasing active
VCC – VO(CANH) – VO(CANL)		 nSTB= VIO, RL = 60 Ω, CL = open
See Figure 7-1 and Figure 7-4 		 –400 400 mV
VOD(DOM) Differential output voltage
Bus biasing active
Dominant		 CANH - CANL nSTB = VIO, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
See Figure 7-1 and Figure 7-4 		 1.5 3 V
CANH - CANL nSTB = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
See Figure 7-1 and Figure 7-4 		 1.4 3.3 V
CANH - CANL nSTB = VIO, TXD = 0 V, RL = 2240 Ω, CL = open
See Figure 7-1 and Figure 7-4 		 1.5 5 V
VOD(REC) Differential output voltage
Bus biasing active
Recessive		 CANH - CANL nSTB = VIO, TXD = VIO, RL = open Ω, CL = open
See Figure 7-1 and Figure 7-4 		 –50 50 mV
VO(STB) Bus output voltage with 
bus biasing inactive
 		 CANH nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open 
See Figure 7-1 and Figure 7-4 
 		 -0.1 0.1 V
CANL nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open
See Figure 7-1 and Figure 7-4 		 -0.1 0.1 V
CANH - CANL nSTB = 0 V, TXD = VIO, RL = open (no load), CL = open
See Figure 7-1 and Figure 7-4 		 -0.2 0.2 V
IOS(DOM) Short-circuit steady-state output current
Bus biasing active
Dominant		 nSTB = VIO, TXD = 0 V
-15 V ≤ V(CANH) ≤ 40 V
See Figure 7-1  and Figure 7-8 		 –100 mA
nSTB = VIO, TXD = 0 V
-15 V ≤ V(CANL) ≤ 40 V
See Figure 7-1  and Figure 7-8 		 100 mA
IOS(REC) Short-circuit steady-state output current
Bus biasing active
Recessive		 nSTB = VIO, VBUS = CANH = CANL
-27 V ≤ VBUS ≤ 42 V
See Figure 7-1  and Figure 7-8 		 –3 3 mA
CAN Receiver Characteristics
VIT(DOM) Receiver dominant state input voltage range
Bus biasing active		 nSTB = VIO, -12 V ≤ VCM ≤ 12 V
See Figure 7-5 and Table 8-6 
 		 0.9 8 V
VIT(REC) Receiver recessive state input voltage range
Bus biasing active		 -3 0.5 V
VHYS Hysteresis voltage for input threshold
Bus biasing active		 nSTB = VIO
See Figure 7-5 and Table 8-6 
 		 140 mV
VDIFF(DOM) Receiver dominant state input voltage range
Bus biasing inactive		 nSTB = 0 V, -12 V ≤ VCM ≤ 12 V
See Figure 7-5 and Table 8-6 
 		 1.150 8 V
VDIFF(REC) Receiver recessive state input voltage range
Bus biasing inactive		 -3 0.4 V
VCM Common mode range nSTB = VIO
See Figure 7-5 and Table 8-6 
 		 –12 12 V
IOFF(LKG) Power-off (unpowered) input leakage current CANH, CANL pins VSUP = 0 V, CANH = CANL = 5 V 2.5 µA
CI Input capacitance to ground (CANH or CANL) (1) 20 pF
CID Differential input capacitance (1) 10 pF
RID Differential input resistance TXD = VCC = VIO = 5 V, nSTB = 5 V
-12 V ≤ VCM ≤ 12 V		 50 100 kΩ
RIN Input resistance (CANH or CANL) 25 50 kΩ
RIN(M) Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%		 V(CANH) = V(CANL) = 5 V –1 1 %
RCBF Valid differential load impedance range for bus fault circuitry RCM = RL, CL = open 45 70 Ω
TXD Characteristics
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current TXD = VIO = 5.5 V –2.5 0 1 µA
IIL Low-level input leakage current TXD = 0 V, VIO = 5.5 V –115 –2.5 µA
ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VSUP = VIO = 0 V –1 0 1 µA
RPU Pull-up resistance to VIO 40 60 80 kΩ
CI Input Capacitance VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V 5 pF
RXD Characteristics
VOH High-level output voltage IO = –2 mA
See Figure 7-5 		 0.8 VIO
VOL Low-level output voltage IO = 2 mA
See Figure 7-5 		 0.2 VIO
ILKG(OFF) Unpowered leakage current RXD = 5.5 V, VSUP = VIO = 0 V -1 1 µA
nSTB Characteristics
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current nSTB = VIO = 5.5 V 0.5 115 µA
IIL Low-level input leakage current nSTB = 0 V, VIO = 5.5 V –1 1 µA
ILKG(OFF) Unpowered leakage current nSTB = 5.5 V, VIO = 0 V –1 0 1 µA
RPD Pull-down resistance 40 60 80 kΩ
nFAULT Characteristics
VOH High-level output voltage IO = -2 mA
 		 0.8 VIO
VOL Low-level output voltage IO = 2 mA
 		 0.2 VIO
ILKG(OFF) Unpowered leakage current nFAULT = 5.5 V, VIO = 0 V –1 0 1 µA
EN Characteristics
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current EN = VCC = VIO = 5.5 V 0.5 115 µA
IIL Low-level input leakage current EN = 0 V, VCC = VIO = 5.5 V -1 1 µA
ILKG(OFF) Unpowered leakage current EN = 5.5 V, VCC = VIO = 0 V -1 1 µA
RPD Pull-down resistance 40 60 80 kΩ
WAKE Characteristics
VIH High-level input voltage Sleep mode VSUP - 2 V
VIL Low-level input voltage VSUP - 3.5 V
IIH High-level input leakage current (2) WAKE = VSUP – 1 V -3 µA
IIL Low-level input leakage current (2) WAKE = 1 V 3 µA
INH Characteristics
ΔVH High-level voltage drop from VSUP to INH (VSUP - VINH) IINH = –6 mA 0.5 1 V
ILKG(INH) Sleep mode leakage current INH = 0 V –0.5 0.5 µA
RPD Pull-down resistance Sleep mode 2.5 4 6 MΩ
(1) Specified by design and verified via bench characterization
(2) To minimize system level current consumption, the WAKE pin will automatically configure itself based on the applied voltage to either an internal pull-up or pull-down current source. A high-level input results in an internal pull-up and a low-level input results in an internal pull-down.