ZHCS616E March 2012 – February 2017 TCA9554
PRODUCTION DATA.
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next. See Table 4.
BIT | I7 | I6 | I5 | I4 | I3 | I2 | I1 | I0 |
DEFAULT | X | X | X | X | X | X | X | X |
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 5.
BIT | O7 | O6 | O5 | O4 | O3 | O2 | O1 | O0 |
DEFAULT | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.
BIT | N7 | N6 | N5 | N4 | N3 | N2 | N1 | N0 |
DEFAULT | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 7.
BIT | C7 | C6 | C5 | C4 | C3 | C2 | C1 | C0 |
DEFAULT | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |