SLASF39 December   2023 TAD5112-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
        4. 7.3.1.4 Phase-Locked Loop (PLL) and Clock Generation
        5. 7.3.1.5 Output Channel Configurations
        6. 7.3.1.6 Reference Voltage
        7. 7.3.1.7 Programmable Microphone Bias
        8. 7.3.1.8 Signal-Chain Processing
          1. 7.3.1.8.1 DAC Signal-Chain
            1. 7.3.1.8.1.1 Programmable Channel Gain and Digital Volume Control
            2. 7.3.1.8.1.2 Programmable Channel Gain Calibration
            3. 7.3.1.8.1.3 Programmable Digital High-Pass Filter
            4. 7.3.1.8.1.4 Programmable Digital Biquad Filters
            5. 7.3.1.8.1.5 Programmable Digital Mixer
            6. 7.3.1.8.1.6 Configurable Digital Interpolation Filters
              1. 7.3.1.8.1.6.1 Linear Phase Filters
                1. 7.3.1.8.1.6.1.1 Sampling Rate: 16 kHz or 14.7 kHz
                2. 7.3.1.8.1.6.1.2 Sampling Rate: 24 kHz or 22.05 kHz
                3. 7.3.1.8.1.6.1.3 Sampling Rate: 32 kHz or 29.4 kHz
                4. 7.3.1.8.1.6.1.4 Sampling Rate: 48 kHz or 44.1 kHz
                5. 7.3.1.8.1.6.1.5 Sampling Rate: 96 kHz or 88.2 kHz
                6. 7.3.1.8.1.6.1.6 Sampling Rate: 384 kHz or 352.8 kHz
        9. 7.3.1.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 TAD5212_P0 Registers
      2. 7.5.2 TAD5212_P1 Registers
      3. 7.5.3 TAD5212_P3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

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6.6 Timing Requirements: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see TBD for timing diagram
MIN NOM MAX UNIT
STANDARD-MODE
fSCL SCL clock frequency 0 100 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs
tLOW Low period of the SCL clock 4.7 μs
tHIGH High period of the SCL clock 4 μs
tSU;STA Setup time for a repeated START condition 4.7 μs
tHD;DAT Data hold time 0 3.45 μs
tSU;DAT Data setup time 250 ns
tr SDA and SCL rise time 1000 ns
tf SDA and SCL fall time 300 ns
tSU;STO Setup time for STOP condition 4 μs
tBUF Bus free time between a STOP and START condition 4.7 μs
FAST-MODE
fSCL SCL clock frequency 0 400 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs
tLOW Low period of the SCL clock 1.3 μs
tHIGH High period of the SCL clock 0.6 μs
tSU;STA Setup time for a repeated START condition 0.6 μs
tHD;DAT Data hold time 0 0.9 μs
tSU;DAT Data setup time 100 ns
tr SDA and SCL rise time 20 300 ns
tf SDA and SCL fall time 20 × (IOVDD / 5.5 V) 300 ns
tSU;STO Setup time for STOP condition 0.6 μs
tBUF Bus free time between a STOP and START condition 1.3 μs
FAST-MODE PLUS
fSCL SCL clock frequency 0 1000 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.26 μs
tLOW Low period of the SCL clock 0.5 μs
tHIGH High period of the SCL clock 0.26 μs
tSU;STA Setup time for a repeated START condition 0.26 μs
tHD;DAT Data hold time 0 μs
tSU;DAT Data setup time 50 ns
tr SDA and SCL Rise Time 120 ns
tf SDA and SCL Fall Time 20 × (IOVDD / 5.5 V) 120 ns
tSU;STO Setup time for STOP condition 0.26 μs
tBUF Bus free time between a STOP and START condition 0.5 μs