ZHCSSV0D November   1995  – February 2024 SN74ACT564

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 说明
  4. Pin Configuration and Functions
  5. Specifications
    1. 4.1 绝对最大额定值
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Thermal Information
    4. 4.4 Electrical Characteristics
    5. 4.5 Timing Requirements
    6. 4.6 Switching Characteristics
    7. 4.7 Operating Characteristics
  6. Parameter Measurement Information
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • NS|20
  • N|20
  • DW|20
  • PW|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

Overview

On the positive transition of the clock (CLK) input, the Q outputs are set to the complements of the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

For specified high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.