SLLSE49D September   2010  – July 2017 SN65HVD1780-Q1 , SN65HVD1781-Q1 , SN65HVD1782-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC
    3. 6.3  ESD Ratings—IEC
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Power Dissipation Ratings
    8. 6.8  Switching Characteristics
    9. 6.9  Package Dissipation Ratings
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bus Fault Conditions
      2. 8.3.2 Receiver Failsafe
      3. 8.3.3 Hot-Plugging
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Bus Loading
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Stub Length
        2. 9.2.2.2 Receiver Failsafe
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 ns, output impedance 50 Ω.

SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0301-02_lls877.gif Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0302-01_lls872.gif Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0303-01_lls872.gif Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0304-01_lls872.gif

NOTE:

D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0305-01_lls872.gif

NOTE:

D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0306-01_lls872.gif Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0307-01_lls872.gif Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
SN65HVD1780-Q1 SN65HVD1781-Q1 SN65HVD1782-Q1 s0308-01_lls872.gif Figure 13. SN65HVD1781 Measurement of Receiver Enable Times With Driver Disabled