ZHCSRX0H September   1983  – March 2023 OP07 , OP07C , OP07D

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Offset-Voltage Null Capability
      2. 7.3.2 Slew Rate
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Swing
        2. 8.2.2.2 Supply and Input Voltage
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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8.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-gain betas (β), collector or emitter resistors, and so on. The input offset pins allow the designer to adjust for these mismatches with external circuitry. Figure 8-1 shows how these input mismatches can be adjusted by putting resistors or a potentiometer between the null pins. Use a potentiometer to fine tune the circuit during testing or for applications that require precision offset control. For more information about designing using the input-offset pins, see the Nulling Input Offset Voltage of Operational Amplifiers application report.

GUID-20230207-SS0I-22WX-DZVC-KBLGPLV66GQQ-low.svg Figure 8-1 Input Offset-Voltage Null Circuit