ZHCSHB5D
January 2018 – January 2021
MSP430FR2422
PRODUCTION DATA
1
特性
2
应用
3
说明
4
功能方框图
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagrams
7.2
Pin Attributes
7.3
Signal Descriptions
7.4
Pin Multiplexing
7.5
Buffer Types
7.6
Connection of Unused Pins
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Active Mode Supply Current Into VCC Excluding External Current
8.5
Active Mode Supply Current Per MHz
8.6
Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
8.7
Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
8.8
Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
8.9
Typical Characteristics - Low-Power Mode Supply Currents
8.10
Typical Characteristics – Current Consumption Per Module
8.11
Thermal Resistance Characteristics
8.12
Timing and Switching Characteristics
8.12.1
Power Supply Sequencing
8.12.1.1
PMM, SVS and BOR
8.12.2
Reset Timing
8.12.2.1
Wake-up Times From Low-Power Modes and Reset
8.12.3
Clock Specifications
8.12.3.1
XT1 Crystal Oscillator (Low Frequency)
8.12.3.2
DCO FLL, Frequency
8.12.3.3
DCO Frequency
8.12.3.4
REFO
8.12.3.5
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
8.12.3.6
Module Oscillator (MODOSC)
8.12.4
Digital I/Os
8.12.4.1
Digital Inputs
8.12.4.2
Digital Outputs
8.12.4.3
Typical Characteristics – Outputs at 3 V and 2 V
8.12.5
VREF+ Built-in Reference
8.12.5.1
VREF+
8.12.6
Timer_A
8.12.6.1
Timer_A
8.12.7
eUSCI
8.12.7.1
eUSCI (UART Mode) Clock Frequency
8.12.7.2
eUSCI (UART Mode)
8.12.7.3
eUSCI (SPI Master Mode) Clock Frequency
8.12.7.4
eUSCI (SPI Master Mode)
8.12.7.5
eUSCI (SPI Slave Mode)
8.12.7.6
eUSCI (I2C Mode)
8.12.8
ADC
8.12.8.1
ADC, Power Supply and Input Range Conditions
8.12.8.2
ADC, 10-Bit Timing Parameters
8.12.8.3
ADC, 10-Bit Linearity Parameters
8.12.9
FRAM
8.12.9.1
FRAM
8.12.10
Debug and Emulation
8.12.10.1
JTAG, Spy-Bi-Wire Interface
8.12.10.2
JTAG, 4-Wire Interface
9
Detailed Description
9.1
Overview
9.2
CPU
9.3
Operating Modes
9.4
Interrupt Vector Addresses
9.5
Bootloader (BSL)
9.6
JTAG Standard Interface
9.7
Spy-Bi-Wire Interface (SBW)
9.8
FRAM
9.9
Memory Protection
9.10
Peripherals
9.10.1
Power-Management Module (PMM)
9.10.2
Clock System (CS) and Clock Distribution
9.10.3
General-Purpose Input/Output Port (I/O)
9.10.4
Watchdog Timer (WDT)
9.10.5
System (SYS) Module
9.10.6
Cyclic Redundancy Check (CRC)
9.10.7
Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
9.10.8
Timers (Timer0_A3, Timer1_A3)
9.10.9
Hardware Multiplier (MPY)
9.10.10
Backup Memory (BAKMEM)
9.10.11
Real-Time Clock (RTC)
9.10.12
10-Bit Analog-to-Digital Converter (ADC)
9.10.13
Embedded Emulation Module (EEM)
9.11
Input/Output Diagrams
9.11.1
Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
9.11.2
Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
9.12
Device Descriptors
9.13
Memory
9.13.1
Memory Organization
9.13.2
Peripheral File Map
9.14
Identification
9.14.1
Revision Identification
9.14.2
Device Identification
9.14.3
JTAG Identification
10
Applications, Implementation, and Layout
10.1
Device Connection and Layout Fundamentals
10.1.1
Power Supply Decoupling and Bulk Capacitors
10.1.2
External Oscillator
10.1.3
JTAG
10.1.4
Reset
10.1.5
Unused Pins
10.1.6
General Layout Recommendations
10.1.7
Do's and Don'ts
10.2
Peripheral- and Interface-Specific Design Information
10.2.1
ADC Peripheral
10.2.1.1
Partial Schematic
10.2.1.2
Design Requirements
10.2.1.3
Layout Guidelines
11
Device and Documentation Support
11.1
Getting Started and Next Steps
11.2
Device Nomenclature
11.3
Tools and Software
11.4
Documentation Support
11.5
支持资源
11.6
Trademarks
11.7
静电放电警告
11.8
Export Control Notice
11.9
术语表
12
Mechanical, Packaging, and Orderable Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
PW|16
RHL|20
散热焊盘机械数据 (封装 | 引脚)
订购信息
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