SNVS481M November   2006  – December 2015 LP3910

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: I2C Interface
    7. 7.7  Electrical Characteristics: Li-Ion Battery Charger
    8. 7.8  Detection and Timing
    9. 7.9  Output Electrical Characteristics: CHG, STAT
    10. 7.10 Output Electrical Characteristics: NRST, IRQB, ONSTAT
    11. 7.11 Input Electrical Characteristics: USBSUSP, USBISEL
    12. 7.12 Input Electrical Characteristics: POWERACK, ONOFF, LDO2EN, BUCK1EN
    13. 7.13 Electrical Characteristics: LDO1 Low Dropout Linear Regulators
    14. 7.14 Electrical Characteristics: LDO2 Low Dropout Linear Regulator
    15. 7.15 Electrical Characteristics: Buck1 Converter
    16. 7.16 Electrical Characteristics: Buck2 Converter
    17. 7.17 Electrical Characteristics: Buck-Boost
    18. 7.18 Electrical Characteristics: ADC
    19. 7.19 I2C Timing Requirements
    20. 7.20 USB Timing Requirements
    21. 7.21 Typical Characteristics
      1. 7.21.1 Battery-Charger Characteristics
      2. 7.21.2 LDO Characteristics
      3. 7.21.3 Buck Characteristics
      4. 7.21.4 Buck-Boost Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Two Buck Converters
      2. 8.1.2 Buck-Boost Converter
      3. 8.1.3 LDO Regulators
      4. 8.1.4 Battery Charger
      5. 8.1.5 ADC
      6. 8.1.6 Supply Specification
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck1, Buck2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.1.1 Buck1, Buck2 Operation
        2. 8.3.1.2 Circuit Operation Description
        3. 8.3.1.3 PWM Operation
        4. 8.3.1.4 Internal Synchronous Rectification
        5. 8.3.1.5 Current Limiting
        6. 8.3.1.6 PFM Operation
      2. 8.3.2  Buck-Boost: Synchronous Buck-Boost Magnetic DC-DC Converter
      3. 8.3.3  Linear Low Dropout Regulators (LDOs)
        1. 8.3.3.1 No-Load Stability
      4. 8.3.4  Li-Ion Linear Charger
        1. 8.3.4.1 Charger Architecture
        2. 8.3.4.2 Charge Status Indication
        3. 8.3.4.3 Thermal Charger Power FET Regulation
        4. 8.3.4.4 Battery Charger Operating Modes
          1. 8.3.4.4.1 Pre-Qualification Mode
          2. 8.3.4.4.2 Full-Rate Charging Mode
          3. 8.3.4.4.3 Constant-Voltage (CV) Charging Mode
          4. 8.3.4.4.4 Top-Off Charging Mode
          5. 8.3.4.4.5 Charge Cycle Complete
        5. 8.3.4.5 Battery Temperature Monitoring (TS Pin)
        6. 8.3.4.6 Disabling Charger
        7. 8.3.4.7 Safety Timer
        8. 8.3.4.8 Charging Maintenance
      5. 8.3.5  ADC
        1. 8.3.5.1 Battery Voltage Measurement
        2. 8.3.5.2 Battery Charge Current Measurement
        3. 8.3.5.3 External General-Purpose Sources
      6. 8.3.6  Interrupt Request Output
        1. 8.3.6.1 Interrupts and Standby Mode
        2. 8.3.6.2 Interrupt Sources
      7. 8.3.7  Power-On-Reset
      8. 8.3.8  Thermal Shutdown and Thermal Alarm
      9. 8.3.9  NRST Pin
      10. 8.3.10 Operation Without I2C Interface
      11. 8.3.11 I2C Master Power Concern
      12. 8.3.12 System Operation When the Load Current Exceeds the USB or Adapter Current Limit
      13. 8.3.13 Power Routing
      14. 8.3.14 Battery Monitor
      15. 8.3.15 External Power and Battery Detection
      16. 8.3.16 USB Suspend Mode
      17. 8.3.17 Setting the USB Current Limit
      18. 8.3.18 Control Registers
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Machine Definitions
        1. 8.4.1.1 Power-Off Mode
        2. 8.4.1.2 Standby Mode
        3. 8.4.1.3 Active Mode
      2. 8.4.2 Mode Sequencing
        1. 8.4.2.1 Power-On, Power-Off Sequencing
        2. 8.4.2.2 Power-On Timing
        3. 8.4.2.3 Power-Off Timing
        4. 8.4.2.4 Transitioning From Standby to Active Mode (Power Up) Battery Power Present Only
        5. 8.4.2.5 Transitioning From Active Mode to Standby Mode
          1. 8.4.2.5.1 External Event Triggers the Transition From Active to Standby Mode
          2. 8.4.2.5.2 Transition From Active to Standby Mode Due to Expiring POWERACK Deadline
          3. 8.4.2.5.3 Transition From Charger Standby Mode to Either Active or Standby Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
        5. 8.5.1.5 Register Write Cycle
        6. 8.5.1.6 Register Read Cycle
        7. 8.5.1.7 Multi-Byte I2C Command Sequence
    6. 8.6 Register Maps
      1. 8.6.1  LDO1 Control Register
      2. 8.6.2  BATTLOW Register (04)H Battery Low Alarm Register
      3. 8.6.3  PON Register (00)H Power-On Event Register
      4. 8.6.4  CHCTL Register (01)H Charger Control Register
      5. 8.6.5  CHSPV Register (02)H Charger Supervisor Register
      6. 8.6.6  ILIMIT Register (03)H Current Limit Register
      7. 8.6.7  ADCC Register (0a)H ADC Control Register
      8. 8.6.8  ADCD Register (0b)H ADC Output Data Register
      9. 8.6.9  IMR Register (0c)H Interrupt Mask Register
      10. 8.6.10 IRQ Register (0d)H Interrupt Request Register
      11. 8.6.11 LDO1 Control Register (08)H
      12. 8.6.12 LDO2 Control Register
      13. 8.6.13 Buck1, Buck2 Control Registers and BUCK1EN Pin
      14. 8.6.14 Buck-Boost Control Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductors for Buck1, Buck2 and Buck-Boost
          1. 9.2.2.1.1 Method 1
          2. 9.2.2.1.2 Method 2
        2. 9.2.2.2 External Capacitors
          1. 9.2.2.2.1 LDO Capacitor Selection
            1. 9.2.2.2.1.1 Input Capacitor
            2. 9.2.2.2.1.2 Output Capacitor
            3. 9.2.2.2.1.3 Capacitor Characteristics
            4. 9.2.2.2.1.4 Noise Bypass Capacitors for VREFH Pin
          2. 9.2.2.2.2 Buck1, Buck2 and Buck-Boost Capacitor Selection
            1. 9.2.2.2.2.1 Input Capacitor Selection for Buck1, Buck2 and Buck-Boost
            2. 9.2.2.2.2.2 Output Capacitor Selection for Buck1, Buck2 and Buck-Boost
        3. 9.2.2.3 Schottky Diode on Charger Input CHG_IN
        4. 9.2.2.4 Resistors
          1. 9.2.2.4.1 Battery Thermistor
          2. 9.2.2.4.2 I2C Pullup Resistors
          3. 9.2.2.4.3 RIREF Resistor
          4. 9.2.2.4.4 RISENSE Resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LDO Regulators
      2. 11.1.2 Buck and Buck-Boost Regulators
    2. 11.2 Layout Example
    3. 11.3 Thermal Performance of the WQFN Package
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

NJV Package
48-Pin WQFN
Top View
LP3910 20212302.gif

Pin Functions

PIN I/O TYPE(1) DESCRIPTION
NO. NAME
1 TS I A Battery temperature sense pin. This pin is normally connected to the thermistor pin of the battery cell.
2 VBATT1 O A Positive battery terminal. This pin must be externally shorted to VBATT2 and VBATT3
3 AGND — G Analog ground
4 VREFH O A Connection to bypass capacitor for internal high reference
5 LDO2EN I D Digital input to enable/disable LDO2
6 VLDO2 O A LDO2 output
7 VIN1 I PWR Power input to LDO1 and LDO2. VIN1 pin must be externally shorted to the VDD pins.
8 VLDO1 O A LDO1 output
9 POWERACK I D Digital power acknowledgement input (see Power-On, Power-Off Sequencing)
10 ISENSE I A A 4.64-kΩ resistor must be connected between this pin and GND. A fraction of the charge current flows through this resistor to enable the ADC to measure the charge current.
11 ADC2 I A Channel 2 input to ADC
12 ADC1 I A Channel 1 input to ADC
13 IRQB O Open Drain Open drain active low interrupt request
14 NRST O Open Drain Open drain active low reset during standby
15 CHG O D This output indicates that a valid charger supply source (USB adapter) has been detected, and the device is charging. (Red LED)
16 STAT O D Battery Status output indicator - off during constant current (CC), 50% duty cycle during constant voltage (CV), 100% duty cycle with a fully charged Li-ion battery (Green LED)
17 BUCK1EN I D Digital input to enable/disable BUCK1
18 VFB1 I A Buck1 Feedback input terminal
19 BCKGND1 — G Buck1 Ground
20 VBUCK1 O A Buck1 Output
21 VIN2 I PWR Power input to Buck1. VIN2 pin must be externally shorted to the VDD pins.
22 VIN3 I PWR Power input to Buck2. VIN3 pin must be externally shorted to the VDD pins.
23 VBUCK2 O A Buck2 Output
24 BCKGND2 — G Buck2 Ground
25 VFB2 I A Buck2 Feedback input terminal
26 ONOFF I D Power ONOFF pin configured either as level (High or Low) triggered or edge (High or Low) triggered.
27 I2C_SCL I D I2C-compatible interface clock terminal
28 VDDIO I D Supply to input / output stages of digital I/O
29 I2C_SDA I/O D I2C-compatible interface data terminal
30 ONSTAT O Open Drain Open Drain output that reflects the debounced state of ONOFF pin.
31 VBBFB I A Buck-Boost Feedback input terminal
32 VBBOUT O A Buck-Boost Output voltage
33 VBBL2 I A Buck-Boost inductor
34 BBGND1 — G Buck-Boost high current ground
35 VBBL1 I A Buck-Boost inductor
36 VIN4 I PWR Power input to Buck-Boost. VIN4 pin must be externally shorted to the VDD pins.
37 USBSUSP I D This pin must be pulled high during USB suspend mode.
38 USBISEL I D Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits the USB charge current to 500 mA.
39 BBGND2 — G BUCK-BOOST Core Ground
40 DGND — G Digital ground
41 VDD3 I PWR Power input to supply application. This pin must be externally shorted to VDD1 and VDD2.
42 VDD2 I PWR Power input to supply application This pin must be externally shorted to VDD1 and VDD3.
43 VBATT3 O A Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2.
44 VBATT2 O A Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3.
45 USBPWR I PWR USB power input pin
46 VDD1 I PWR Power input to supply application This pin is shorted to VDD2 and VDD3.
47 CHG_DET I A Wall adapter power input pin
48 IREF I A A 121-kΩ resistor must be connected between this pin and AGND. The resistor value determines the reference current for the internal bias generator.
(1) A: Analog; D: Digital: G: Ground; PWR: Power