SNVS336F June   2006  – August 2015 LP38856

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable Operation
      2. 7.3.2 Input Voltage
      3. 7.3.3 Bias Voltage
      4. 7.3.4 Undervoltage Lockout
      5. 7.3.5 Supply Sequencing
      6. 7.3.6 Reverse Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with 3 V ≤ VBIAS ≤ 5.5 V , VOUT(TARGET) + 0.3 V ≤ VIN ≤ VBIAS
      2. 7.4.2 Operation with VEN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Output Capacitor
          2. 8.2.2.1.2 Input Capacitor
          3. 8.2.2.1.3 Bias Capacitor
        2. 8.2.2.2 Power Dissipation and Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Power dissipation(3) Internally limited
VIN Supply voltage (survival) –0.3 6 V
VBIAS Supply voltage (survival) –0.3 6 V
VEN Voltage (survival) –0.3 6 V
VOUT Voltage (survival) –0.3 6 V
IOUT Current (survival) Internally Limited
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
(3) Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VIN Supply voltage (VOUT + VDO) VBIAS
VBIAS Supply voltage 3 5.5 V
VEN Enable input voltage 0.0 VBIAS
IOUT Output current 0 3 mA/A
Junction temperature range(2) –40 125 °C
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits (see Electrical Characteristics). Specifications do not apply when operating the device outside of its rated operating conditions.
(2) Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See Application and Implementation for details.

6.4 Thermal Information

THERMAL METRIC(1) LP38856 UNIT
KTT (DDPAK/TO-263) NDH (TO-220)
5 PINS
RθJA Junction-to-ambient thermal resistance 41.8 32.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.0 43.8 °C/W
RθJB Junction-to-board thermal resistance 24.8 18.6 °C/W
ψJT Junction-to-top characterization parameter 13.1 8.8 °C/W
ψJB Junction-to-board characterization parameter 23.8 18.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, VEN = VBIAS. Limits apply for TJ = 25°C only unless otherwise specified. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output Voltage Tolerance VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS
3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A		 –1% 0% +1%
VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS
3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3 A
TJ = –40°C to 125°C		 –3% 3%
VOUT(NOM) + 1V ≤ VIN ≤ VBIAS
3 V ≤ VBIAS ≤ 5.5 V, 10 mA ≤ IOUT ≤ 3.0A
0°C ≤ TJ ≤ 125°C		 –2% 0% 2%
ΔVOUT/ΔVIN Line regulation, VIN(1) VOUT(NOM) + 1 V ≤ VIN ≤ VBIAS 0.04 %/V
ΔVOUT/ΔVBIAS Line regulation, VBIAS(1) 3 V ≤ VBIAS ≤ 5.5 V 0.10 %/V
ΔVOUT/ΔIOUT Output voltage load regulation(2) 10 mA ≤ IOUT ≤ 3 A 0.2 %/A
VDO Dropout voltage, VIN − VOUT(3) IOUT = 3 A 240 300 mV
IOUT = 3 A, TJ = –40°C to 125°C 450
IGND(IN) Ground pin current drawn from VIN supply LP38856-0.8: 10 mA ≤ IOUT ≤ 3 A 7 8.5 mA
LP38856-0.8: 10 mA ≤ IOUT ≤ 3 A
TJ = –40°C to 125°C		 9
LP38856-1.2: 10 mA ≤ IOUT ≤ 3 A 11 12
LP38856-1.2: 10 mA ≤ IOUT ≤ 3 A
TJ = –40°C to 125°C		 15
VEN ≤ 0.5 V 1 10 µA
VEN ≤ 0.5 V, TJ = –40°C to 125°C 300
IGND(BIAS) Ground pin current drawn from VBIAS supply 10 mA ≤ IOUT ≤ 3 A 3 3.8 mA
10 mA ≤ IOUT ≤ 3 A
TJ = –40°C to 125°C		 4.5
VEN ≤ 0.5 V 100 170 µA
VEN ≤ 0.5 V, TJ = –40°C to 125°C 200
UVLO Undervoltage lock-out threshold VBIAS rising until device is functional 2.20 2.45 2.70 V
VBIAS rising until device is functional
TJ = –40°C to 125°C		 2 2.9
UVLO(HYS) Undervoltage lock-out hysteresis VBIAS falling from UVLO threshold until device is non-functional 60 150 300 mV
50 350
ISC Output short-circuit current VIN = VOUT(NOM) + 1 V,
VBIAS = 3 V VOUT = 0 V		 6.2 A
ENABLE PIN
IEN ENABLE pin current VEN = VBIAS 0.01 µA
VEN = 0 V, VBIAS = 5.5 V –19 –30 –40
VEN = 0 V, VBIAS = 5.5 V
TJ = –40°C to 125°C		 –13 –51
VEN(ON) Enable voltage threshold VEN rising until Output = ON 1 1.25 1.50 V
VEN rising until Output = ON
TJ = –40°C to 125°C		 0.9 1.55
VEN(HYS) Enable voltage hysteresis VEN falling from VEN(ON) until Output = OFF 50 100 150 mV
VEN falling from VEN(ON) until Output = OFF
TJ = –40°C to 125°C		 30 200
tOFF Turn-OFF delay time RLOAD × COUT << tOFF 20 µs
tON Turn-ON delay time RLOAD × COUT << tON 15
AC PARAMETERS
PSRR (VIN) Ripple rejection for VIN input voltage VIN = VOUT +1 V, ƒ = 120 Hz 80 dB
VIN = VOUT + 1V, ƒ = 1 kHz 65
PSRR (VBIAS) Ripple rejection for VBIAS voltage VBIAS = VOUT + 3 V, ƒ = 120 Hz 58 dB
VBIAS = VOUT + 3 V, ƒ = 1 kHz 58
en Output noise density ƒ = 120 Hz 1 µV/√Hz
Output noise voltage BW = 10 Hz − 100 kHz 150 µV(RMS)
BW = 300 Hz − 300 kHz 90
THERMAL PARAMETERS
TSD Thermal shutdown junction temperature 160 °C
TSD(HYS) Thermal shutdown hysteresis 10
(1) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(2) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.
(3) Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop no more than 2% from the nominal value

6.6 Typical Characteristics

Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-µF ceramic, CBIAS = 1-µF ceramic, VEN = VBIAS.
LP38856 20131187.png
Figure 1. VBIAS Ground Pin Current (IGND(BIAS))
vs VBIAS
LP38856 20131162.png
Figure 3. VIN Ground Pin Current (IGND(IN)) vs Temperature
LP38856 20131165.png
Figure 5. Dropout Voltage (VDO) vs Temperature
LP38856 20131167.png
Figure 7. VOUT vs Temperature
LP38856 20131172.png
Figure 9. Enable Thresholds (VEN) vs Temperature
LP38856 20131174.png
Figure 11. Enable Pull-Up Resistor (REN) vs Temperature
LP38856 20131179.png
Figure 13. VBIAS Line Transient Response
LP38856 20131181.png
Figure 15. Load Transient Response, COUT = 10-μF Ceramic
LP38856 20131184.png
COUT = 100-μF Ceramic
Figure 17. Load Transient Response
LP38856 20131186.png
COUT = 100-μF Tantalum
Figure 19. Load Transient Response
LP38856 20131171.png
Figure 21. VIN PSRR
LP38856 20131161.png
Figure 2. VBIAS Ground Pin Current (IGND(BIAS))
vs Temperature
LP38856 20131163.png
Figure 4. Load Regulation vs Temperature
LP38856 20131166.png
Figure 6. Output Current Limit (ISC) vs Temperature
LP38856 20131168.png
Figure 8. UVLO Thresholds vs Temperature
LP38856 20131173.png
Figure 10. Enable Pull-Down Current (IEN) vs Temperature
LP38856 20131177.png
Figure 12. VIN Line Transient Response
LP38856 20131180.png
Figure 14. VBIAS Line Transient Response
LP38856 20131183.png
COUT = 100-μF Ceramic
Figure 16. Load Transient Response
LP38856 20131185.png
COUT = 100-μF Tantalum
Figure 18. Load Transient Response
LP38856 20131170.png
Figure 20. VBIAS PSRR
LP38856 20131169.png
Figure 22. Output Noise