SNOSA40K November   2002  – December 2016 LP2996-N , LP2996A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up
      2. 7.4.2 Normal Operation
      3. 7.4.3 Shutdown
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical SSTL-2 Application Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Input Capacitor
          2. 8.2.1.2.2 Output Capacitor
            1. 8.2.1.2.2.1 Aluminum Electrolytics
            2. 8.2.1.2.2.2 Ceramic Capacitors
            3. 8.2.1.2.2.3 Hybrid Capacitors
            4. 8.2.1.2.2.4 PC Application Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Other Application Circuits
        1. 8.2.2.1 SSTL-2 Applications
        2. 8.2.2.2 DDR-II Applications
        3. 8.2.2.3 DDR-III Applications
      3. 8.2.3 Level Shifting
      4. 8.2.4 HSTL Applications
      5. 8.2.5 QDR Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LP2996 has split rails to allow flexibility in powering the device. It has a control circuitry rail (AVIN) and an output power stage rail (PVIN), both separate from the reference voltage input (VDDQ). This allows for different setups which cater to specific requirements such as high current capabilities, lower thermal dissipation, or minimum component count. Because the output is always VDDQ / 2 due to two internal 50-kΩ resistors, the only necessary external components are bypass capacitors.

Typical Applications

Typical SSTL-2 Application Circuit

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where VTT is distributed across a long plane, it is advisable to use multiple bulk capacitors and addition to high frequency decoupling.

LP2996-N LP2996A 20057518.gif Figure 18. Typical SSTL-2 Application Circuit Diagram

Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

PARAMETER VALUE
VDDQ 1.5 V
Input to AVIN and PVIN, VDD 2.5 V
VREF 0.75 V
VTT 0.75 V
Input bypass capacitor, CIN 47 µF
Output bypass capacitor, COUT 220 µF

Detailed Design Procedure

The LP2996 requires voltage be applied to three pins for proper operation: VDDQ, AVIN, and PVIN. VDDQ sets the internal reference voltage and is divided across two 50-kΩ resistors. Therefore, VDDQ must be set at exactly twice the appropriate DDR termination. AVIN powers the internal control circuitry and must be from 2.2 V to
5.5 V. PVIN is the supply for the power output stage and must be larger than or equal to VDDQ while smaller than or equal to AVIN. When picking PVIN, note that smaller values reduce internal power dissipation but reduce the maximum continuous current as well. It is acceptable to tie PVIN to either VDDQ or AVIN to minimize the number of supplies and bypass capacitors required.

To prevent voltage dips on the output, a bypass capacitor must be placed on the VTT line. The size of this capacitor does not affect stability, but larger values improve the transient response and must be sized according to the design requirements. When using ceramic capacitors on the output, large load steps can cause ringing on VTT. Table 2 shows the range of acceptable equivalent series resistance (ESR) that can be added to dampen and improve the response.

Table 2. Approximate ESR Values for VTT Capacitors

VTT CAPACITANCE (µF) RECOMMENDED ESR (mΩ)
100 50
150 42
220 36
330 30

Another bypass capacitor on PVIN is recommended to keep current spikes from pulling down the input voltage. This is especially important if PVIN and VDDQ are on the same supply. A small 0.01-µF capacitor can be placed on VREF to reduce noise. VSENSE provides a feedback path necessary for regulating the output voltage; Therefore, it must be connected to VTT. If a long VSENSE trace is necessary, a small ceramic capacitor may be required to filter out any high frequency noise picked up from switching I/O signals.

Input Capacitor

The LP2996-N and LP2996A do not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor must be placed as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for aluminum electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value approximately 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2996-N or LP2996A is placed close to the bulk capacitance from the output of the 2.5-V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47-µF capacitor must be placed as close to possible to the PVIN rail. An additional 0.1-µF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device.

Output Capacitor

The LP2996-N and LP2996A have been designed to be insensitive of output capacitor size or ESR. This allows the flexibility to use any capacitor desired. The choice for output capacitor is determined solely on the application and the requirements for load transient response of VTT. TI recommends the output capacitor be sized above
100 µF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR is determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are discussed: Aluminum Electrolytics, Ceramic Capacitors, and Hybrid Capacitors.

Aluminum Electrolytics

Aluminum electrolytics often only specify impedance at a frequency of 120 Hz, indicating poor high frequency performance. Only aluminum electrolytics that specified an impedance at higher frequencies, from 20 kHz to
100 kHz, must be used for the LP2996-N and LP2996A. To improve the ESR, many aluminum electrolytics may be combined in parallel for an overall reduction. Be aware of the extent at which the ESR changes over temperature. Aluminum electrolytic capacitors' ESR may rapidly increase at cold temperatures.

Ceramic Capacitors

Ceramic capacitors typically have a low capacitance, from 10 µF to 100 µF, but they have excellent AC performance for bypassing noise due to very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance, TI recommends using ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. TI recommends dielectric of X5R or better for all ceramic capacitors.

Hybrid Capacitors

Hybrid capacitors offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than any other capacitor.

PC Application Considerations

With motherboards and other applications where VTT is distributed across a long plane, it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. Figure 19 shows an example circuit where two bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost.

In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitors approximately 1000 µF are typically used.

LP2996-N LP2996A 20057519.gif Figure 19. Typical SSTL-2 Application Circuit for Motherboards

Application Curves

LP2996-N LP2996A 0.5A_Load_Transient_220uF_Vtt_Capacitor.png Figure 20. 0.5-A Load Transient With 220-µF VTT Capacitor
LP2996-N LP2996A 1.5A_Load_Transient_220uF_Vtt_Capacitor.png Figure 21. 1.5-A Load Transient With 220-µF VTT Capacitor

Other Application Circuits

Several different application circuits are shown to illustrate some of the options that are possible in configuring the LP2996-N or LP2996A.

SSTL-2 Applications

For the majority of applications that implement the SSTL-2 termination scheme, TI recommends connecting all the input rails to the 2.5-V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 22.

LP2996-N LP2996A 20057510.gif Figure 22. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern, then the LP2996-N or LP2996A has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8 V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5 V, 3.3 V, or 5 V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients are encountered.

LP2996-N LP2996A 20057511.gif Figure 23. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8-V rail is not available and it is not desirable to use 2.5 V, is to connect the LP2996-N or LP2996A power rail to 3.3 V. In this situation AVIN is limited to operation on the 3.3-V or 5-V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Prevent the device from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk, TI recommends not supplying the output stage with a voltage higher than a nominal 3.3-V rail.

LP2996-N LP2996A 20057512.gif Figure 24. SSTL-2 Implementation with Higher Voltage Rails

DDR-II Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N and LP2996A in applications utilizing DDR-II memory. Figure 25 and Figure 26 show implementations of recommended circuit configurations for DDR-II applications. The output stage is connected to the 1.8-V rail and the AVIN pin can be connected to either a 3.3-V or 5-V rail. TI recommends the LP2996A, LP2998, or LP2998-Q1 for DDR-III and DDR-III low power designs.

LP2996-N LP2996A 20057513.gif Figure 25. Recommended DDR-II Termination

If it is not desirable to use the 1.8-V rail it is possible to connect the output stage to a 3.3-V rail. Take care not to exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason, TI does not recommend powering PVIN from a rail higher than the nominal 3.3 V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.

LP2996-N LP2996A 20057514.gif Figure 26. DDR-II Termination with Higher Voltage Rails

DDR-III Applications

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996A in applications utilizing DDR-III memory. The output stage is connected to the 1.5-V rail and the AVIN pin can be connected to a 2.2-V to 5.5-V rail.

LP2996-N LP2996A new_image_DDR3_snosa40.gif Figure 27. Recommended DDR-III Termination Using the LP2996A

If it is not desirable to use the 1.5-V to 2.5-V rail it is possible to connect the output stage to a 3.3-V rail. Do not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason, TI recommends not to power PVIN off a rail higher than the nominal 3.3-V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current.

Level Shifting

If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than VDDQ / 2 for regulating the output voltage. Several options are available to scale the output to any voltage required. One method is to level shift the output by using feedback resistors from VTT to the VSENSE pin. This is shown in Figure 28 and Figure 29. Figure 28 shows how to use two resistors to level shift VTT above the internal reference voltage of VDDQ / 2. Calculate the exact voltage at VTT with Equation 1.

Equation 1. LP2996-N LP2996A equation_01_snos40.gif
LP2996-N LP2996A 20057515.gif Figure 28. Increasing VTT by Level Shifting

Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ / 2. Equation 2 shows the relation of VTT to the resistors.

Equation 2. LP2996-N LP2996A equation_02_snos40.gif
LP2996-N LP2996A 20057516.gif Figure 29. Decreasing VTT by Level Shifting

HSTL Applications

The LP2996-N and LP2996A can be easily adapted for HSTL applications by connecting VDDQ to the 1.5-V rail. This produces a VTT and VREF voltage of approximately 0.75 V for the termination resistors. AVIN and PVIN must be connected to a 2.5-V rail for optimal performance.

LP2996-N LP2996A 20057517.gif Figure 30. HSTL Application

QDR Applications

Quad data rate (QDR) applications use multiple channels for improved memory performance. However, this increase in bus lines increases the current levels required for termination. TI recommends using a dedicated LP2996-N or LP2996A for each channel to terminate multiple channels. This simplifies layout and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or one of the LP2996-N or LP2996A signals. Because VREF and VTT are expected to track and the part to part variations are minor, there must be little difference between the reference signals of each device.