SNOSAW6E January   2008  – December 2014 LMP7721

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: 2.5 V
    6. 6.6 Electrical Characteristics: 5 V
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Ultra-Low Input Bias Current
      2. 7.3.2 Wide Bandwidth at Low-Supply Current
      3. 7.3.3 Low Input Referred Noise
      4. 7.3.4 Low-Supply Voltage
      5. 7.3.5 Rail-to-Rail Output and Ground Sensing
      6. 7.3.6 Unique Pinout
      7. 7.3.7 Input Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Compensating Input Capacitance
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Using a Guard
      2. 8.1.2 Use Triaxial Cable
      3. 8.1.3 Properly Clean the Assembly
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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10 Layout

10.1 Layout Guidelines

In order to capitalize on the LMP7721’s ultra-low input bias current, careful circuit layout and assembly are required. Guarding techniques are highly recommended to reduce parasitic leakage current by isolating the LMP7721’s input from large voltage gradients across the PC board. A guard is a low-impedance conductor that surrounds an input line and its potential is raised to the input line’s voltage. The input pins should be fully guarded as shown in Figure 54. The guard traces should completely encircle the input connections. In addition, they should be located on both sides of the PCB and be connected together.

To further guard the inputs from the supply pins, the two N/C pins may be connected to the guard trace which will provide guarding down to the leadframe level.

Solder mask should not cover the input and the guard area including guard traces on either side of the PCB.

Keep switching power supplies and other noise-producing devices away from the input area.

10.2 Layout Example

Layout.gifFigure 54. Layout Example Showing Guard Trace