ZHCSGL2E December   2016  – December 2023 LMK62A2-100M , LMK62A2-150M , LMK62A2-156M , LMK62A2-200M , LMK62A2-266M , LMK62E0-156M , LMK62E2-100M , LMK62E2-156M , LMK62I0-100M , LMK62I0-156M

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Supply
    6. 5.6  LVPECL Output Characteristics
    7. 5.7  LVDS Output Characteristics
    8. 5.8  HCSL Output Characteristics
    9. 5.9  OE Input Characteristics
    10. 5.10 Frequency Tolerance Characteristics
    11. 5.11 Power-On/Reset Characteristics (VDD)
    12. 5.12 PSRR Characteristics
    13. 5.13 PLL Clock Output Jitter Characteristics
    14. 5.14 Additional Reliability and Qualification
  7. 6 Parameter Measurement Information
    1. 6.1 Device Output Configurations
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
        1. 7.2.1.1 Ensuring Thermal Reliability
        2. 7.2.1.2 Best Practices for Signal Integrity
        3. 7.2.1.3 Recommended Solder Reflow Profile
  9. 8 Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • SIA|6
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.4 Thermal Information

THERMAL METRIC(1)LMK62XX (2) (3) (4)UNIT
SIA (QFM )
6 PINS
Airflow (LFM) 0
RθJAJunction-to-ambient thermal resistance94.5°C/W
RθJC(top)Junction-to-case (top) thermal resistance65.1°C/W
RθJBJunction-to-board thermal resistance59°C/W
ψJTJunction-to-top characterization parameter23.3°C/W
ψJBJunction-to-board characterization parameter64.1°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistancen/a°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal resistance is calculated on a 4-layer JEDEC board.
(3) Connected to GND with 2 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality.