SNAS745 June 2017 LM555-MIL
PRODUCTION DATA.
10 Layout
10.1 Layout Guidelines
Standard PCB rules apply to routing the LM555-MIL. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitor should be as close as possible to the LM555-MIL. The capacitor used for the time delay should also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.
Figure 20 is the basic layout for various applications.
- C1 – based on time delay calculations
- C2 – 0.01-µF bypass capacitor for control voltage pin
- C3 – 0.1-µF bypass ceramic capacitor
- C4 – 1-µF electrolytic bypass capacitor
- R1 – based on time delay calculations
- U1 – LMC555
10.2 Layout Example
Figure 20. Layout Example