ZHCSEV7I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 支持资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.2 Start-Up and UVLO

The start-up voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present thereafter.

The LM5113 requires an external bootstrap diode with a 20-Ω series resistor to charge the high-side supply on a cycle-by-cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or LL4148.

The LM5113 has an Undervoltage Lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also if there is insufficient VDD voltage, the UVLO will actively pull the LOL and HOL low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.

Table 1. VDD UVLO Feature Logic Operation

CONDITION (VHB-HS > VHBR for all cases below) HI LI HO LO
VDD - VSS < VDDR during device start-up H L L L
VDD - VSS < VDDR during device start-up L H L L
VDD - VSS < VDDR during device start-up H H L L
VDD - VSS < VDDR during device start-up L L L L
VDD - VSS < VDDR - VDDH after device start-up H L L L
VDD - VSS < VDDR - VDDH after device start-up L H L L
VDD - VSS < VDDR - VDDH after device start-up H H L L
VDD - VSS < VDDR - VDDH after device start-up L L L L

Table 2. VHB-HS UVLO Feature Logic Operation

CONDITION (VDD > VDDR for all cases below) HI LI HO LO
VHB-HS < VHBR during device start-up H L L L
VHB-HS < VHBR during device start-up L H L H
VHB-HS < VHBR during device start-up H H L H
VHB-HS < VHBR during device start-up L L L L
VHB-HS < VHBR - VHBH after device start-up H L L L
VHB-HS < VHBR - VHBH after device start-up L H L H
VHB-HS < VHBR - VHBH after device start-up H H L H
VHB-HS < VHBR - VHBH after device start-up L L L L