ZHCSCT1A April   2014  – August 2014 LM5066I

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 简化电路原理图
  5. 修订历史记录
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Handling Ratings
    2. 8.2 Recommended Operating Conditions
    3. 8.3 Thermal Information
    4. 8.4 Electrical Characteristics
    5. 8.5 SMBus Communications Timing Requirements and Definitions
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit
      2. 9.3.2 Circuit Breaker
      3. 9.3.3 Power Limit
      4. 9.3.4 UVLO
      5. 9.3.5 OVLO
      6. 9.3.6 Power Good Pin
      7. 9.3.7 VDD Sub-Regulator
      8. 9.3.8 Remote Temperature Sensing
      9. 9.3.9 Damaged MOSFET Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up Sequence
      2. 9.4.2 Gate Control
      3. 9.4.3 Fault Timer and Restart
      4. 9.4.4 Shutdown Control
      5. 9.4.5 Enabling/Disabling and Resetting
    5. 9.5 Programming
      1. 9.5.1 PMBus Command Support
      2. 9.5.2 Standard PMBus Commands
        1. 9.5.2.1  OPERATION (01h)
        2. 9.5.2.2  CLEAR_FAULTS (03h)
        3. 9.5.2.3  CAPABILITY (19h)
        4. 9.5.2.4  VOUT_UV_WARN_LIMIT (43h)
        5. 9.5.2.5  OT_FAULT_LIMIT (4Fh)
        6. 9.5.2.6  OT_WARN_LIMIT (51h)
        7. 9.5.2.7  VIN_OV_WARN_LIMIT (57h)
        8. 9.5.2.8  VIN_UV_WARN_LIMIT (58h)
        9. 9.5.2.9  STATUS_BYTE (78h)
        10. 9.5.2.10 STATUS_WORD (79h)
        11. 9.5.2.11 STATUS_VOUT (7Ah)
        12. 9.5.2.12 STATUS_INPUT (7Ch)
        13. 9.5.2.13 STATUS_TEMPERATURE (7dh)
        14. 9.5.2.14 STATUS_CML (7Eh)
        15. 9.5.2.15 STATUS_OTHER (7Fh)
        16. 9.5.2.16 STATUS_MFR_SPECIFIC (80h)
        17. 9.5.2.17 READ_EIN (86h)
        18. 9.5.2.18 READ_VIN (88h)
        19. 9.5.2.19 READ_IIN (89h)
        20. 9.5.2.20 READ_VOUT (8Bh)
        21. 9.5.2.21 READ_TEMPERATURE_1 (8Dh)
        22. 9.5.2.22 READ_PIN (97h)
        23. 9.5.2.23 MFR_ID (99h)
        24. 9.5.2.24 MFR_MODEL (9Ah)
        25. 9.5.2.25 MFR_REVISION (9Bh)
      3. 9.5.3 Manufacturer Specific PMBus Commands
        1. 9.5.3.1  MFR_SPECIFIC_00: READ_VAUX (D0h)
        2. 9.5.3.2  MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
        3. 9.5.3.3  MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
        4. 9.5.3.4  MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
        5. 9.5.3.5  MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
        6. 9.5.3.6  MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
        7. 9.5.3.7  MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
        8. 9.5.3.8  MFR_SPECIFIC_07: GATE_MASK (D7h)
        9. 9.5.3.9  MFR_SPECIFIC_08: ALERT_MASK (D8h)
        10. 9.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
        11. 9.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
        12. 9.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
        13. 9.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
        14. 9.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
        15. 9.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
        16. 9.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)
        17. 9.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN
        18. 9.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
        19. 9.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
        20. 9.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
      4. 9.5.4 Reading and Writing Telemetry Data and Warning Thresholds
      5. 9.5.5 Determining Telemetry Coefficients Empirically With Linear Fit
      6. 9.5.6 Writing Telemetry Data
      7. 9.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)
      8. 9.5.8 SMBA Response
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 48-V, 10-A PMBus Hotswap Design
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design-In Procedure
          1. 10.2.1.2.1 Select RSNS and CL Setting
          2. 10.2.1.2.2 Selecting the Hotswap FETs
          3. 10.2.1.2.3 Select Power Limit
          4. 10.2.1.2.4 Set Fault Timer
          5. 10.2.1.2.5 Check MOSFET SOA
          6. 10.2.1.2.6 Set UVLO and OVLO Thresholds
            1. 10.2.1.2.6.1 Option A
            2. 10.2.1.2.6.2 Option B
            3. 10.2.1.2.6.3 Option C
            4. 10.2.1.2.6.4 Option D
          7. 10.2.1.2.7 Power Good Pin
          8. 10.2.1.2.8 Input and Output Protection
          9. 10.2.1.2.9 Final Schematic and Component Values
        3. 10.2.1.3 Application Curves
      2. 10.2.2 48-V, 20-A PMBus Hotswap Design
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1  Selecting the Sense Resistor and CL Setting
          2. 10.2.2.2.2  Selecting the Hotswap FETs
          3. 10.2.2.2.3  Select Power Limit
          4. 10.2.2.2.4  Set Fault Timer
          5. 10.2.2.2.5  Check MOSFET SOA
          6. 10.2.2.2.6  Switching to dv/dt-Based Start-Up
          7. 10.2.2.2.7  Choosing the VOUT Slew Rate
          8. 10.2.2.2.8  Select Power Limit and Fault Timer
          9. 10.2.2.2.9  Chose Input and Output Protection and Set Undervoltage, Overvoltage, and Power Good Thresholds
          10. 10.2.2.2.10 Final Schematic and Component Values
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Detailed Description

9.1 Overview

The inline protection functionality of the LM5066I is designed to control the in-rush current to the load after insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage and the dV/dt of the voltage applied to the load. The effects on other circuits in the system are minimized by preventing possible unintended resets. When the circuit card is removed, a controlled shutdown can be implemented using the LM5066I.

In addition to a programmable current limit, the LM5066I monitors and limits the maximum power dissipation in the series-pass device to maintain operation within the device safe operating area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series-pass device. In this event, the LM5066I can latch off or repetitively retry based on the hardware setting of the RETRY pin. When started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly switches off the series-pass device upon detection of a severe overcurrent condition. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066I when the system input voltage is outside the desired operating range.

The telemetry capability of the LM5066I provides intelligent monitoring of the input voltage, output voltage, input current, input power, temperature, and an auxiliary input. The LM5066I also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power, and temperature through the PMBus interface. Additionally, the LM5066I is capable of detecting damage to the external MOSFET, Q1.

9.2 Functional Block Diagram

Fig13_BD_LM5066I.gif

9.3 Feature Description

9.3.1 Current Limit

The current limit threshold is reached when the voltage across the sense resistor RSNS (VIN_K to SENSE) exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5066I resumes usual operation. If the current limit condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper operation, the RSNS resistor value should be no higher than 200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).

9.3.2 Circuit Breaker

If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q1 is quickly switched off by the 160-mA pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across RSNS falls below the circuit breaker (CB) threshold, the 160-mA pulldown current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.2-mA pulldown current at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register.

9.3.3 Power Limit

An important feature of the LM5066I is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5066I determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the RSNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled using the ALERT_MASK (D8h) register.

9.3.4 UVLO

The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range defined by the programmable UVLO and OVLO levels. Typically the UVLO level at VIN is set with a resistor divider. Referring to the Functional Block Diagram when VIN is below the UVLO level, the internal 20-µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the 4.2-mA pulldown current at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q1 is switched on by the 20-µA current source at the GATE pin if the insertion time delay has expired.

See the Application and Implementation section for a procedure to calculate the values of the threshold setting resistors. The minimum possible UVLO level at VIN can be set by connecting the UVLO/EN pin to VIN. In this case, Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up, an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.

9.3.5 OVLO

The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range defined by the programmable UVLO and OVLO levels. If VIN raises the OVLO pin voltage above its threshold, Q1 is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When VIN is reduced below the OVLO level Q1 is re-enabled. An OVLO condition toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.

See the Application and Implementation section for a procedure to calculate the threshold setting resistor values.

9.3.6 Power Good Pin

The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.

9.3.7 VDD Sub-Regulator

The LM5066I contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V rail used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in order to protect the LM5066I in the event of a short. The sub-regulator requires a ceramic bypass capacitance having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows.

9.3.8 Remote Temperature Sensing

The LM5066I is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066I ground. Place the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The temperature is measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement. Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). By default, the temperature fault and warning thresholds of the LM5066I are set to 256°C and are effectively disabled. These thresholds can be reprogrammed through the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the LM5066I are not used, the DIODE pin should be grounded.

Erroneous temperature measurements may result when the device input voltage is below the minimum operating voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures, this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q1. In this case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION (03h) register.

9.3.9 Damaged MOSFET Detection

The LM5066I is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted because of damage present between the drain and gate and/or drain and source.

9.4 Device Functional Modes

9.4.1 Power-Up Sequence

The VIN operating range of the LM5066I is 10 to 80 V, with a transient capability to 100 V. Referring to the 简化电路原理图 and Figure 13, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 160-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8-µA current source, and Q1 is held off by a 4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 3.9 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then switches on Q1 when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the insertion time, Q1 the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1. The maximum voltage from the gate to source of the Q1 is limited by an internal 16.5-V Zener diode.

As the voltage at the OUT pin increases, the LM5066I monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 13), an internal 75-µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 3.9 V, the 75-µA current source is switched off, and CT is discharged by the internal 2.5-µA current sink (t3 in Figure 13). The in-rush limiting no longer engages unless a current-limit condition occurs.

If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t2, a fault is declared and Q1 is turned off. See the Fault Timer and Restart section for a complete description of the fault mode.

The LM5066I asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device operation and remains high until a CLEAR_FAULTS command is received.

Fig14_PowerUp_66i.gifFigure 13. Power-Up Sequence (Current Limit Only)

9.4.2 Gate Control

A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q1). During normal operating conditions (t3 in Figure 13), the gate of Q1 is held charged by an internal 20-µA current source. The charge pump peak voltage is roughly 13.5 V, which forces a VGS across Q1 of 13.5 V under normal operation. When the system voltage is initially applied, the GATE pin is held low by a 160-mA pulldown current. This helps prevent an inadvertent turn-on of Q1 through its drain-gate capacitance as the applied system voltage increases.

During the insertion time (t1 in Figure 13) the GATE pin is held low by a 4.2-mA pulldown current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2 in Figure 13 the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 3.9 V during t2, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE pin is then held low until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin to GROUND or floating). See the Fault Timer and Restart section. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 4.2-mA pulldown current to switch off Q1.

9.4.3 Fault Timer and Restart

When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, a 75-µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 13 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 3.9 V, the LM5066I returns to the normal operating mode and CT is discharged by the 1.5-mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q1 is switched off by a 4.2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry configuration.

If the RETRY pin is high, the LM5066I latches the GATE pin low at the end of the fault timeout period. CT is then discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current until a power-up sequence is externally initiated by cycling the input voltage (VIN), or momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 14. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register remains high while the latched off condition persists.

Fig15_Restart.gifFigure 14. Latched Fault Restart Control

The LM5066I provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9 and 1.2 V seven times after the fault timeout period, as shown in Figure 15. The period of each cycle is determined by the 75-µA charging current, the 2.5-µA discharge current, and the value of the capacitor, CT. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 20-µA current source at the GATE pin turns on Q1. If the fault condition is still present, the fault timeout period and the restart sequence repeat. The RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16, or infinite may be selected by setting the appropriate bits in the DEVICE_SETUP (D9h) register.

Fig16_RestartSeq_66i.gifFigure 15. Restart Sequence

9.4.4 Shutdown Control

The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open-drain device, as shown in Figure 16. When UVLO/EN pin is released, the LM5066I switches on the FET with in-rush current and power limiting.

Fig17_ShutDown.gifFigure 16. Shutdown Control

9.4.5 Enabling/Disabling and Resetting

The output can be disabled at during normal operation by either pulling the UVLO/EN pin to below its threshold or the OVLO pin above its threshold. This will cause the GATE voltage to be forced low with a pulldown strength of 4.2 mA. Toggling the UVLO/EN pin also resets the LM5066I from a latched-off state due to an overcurrent or over-power limit condition that caused the maximum allowed number of retries to be exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the volatile memory or address location of the LM5066I. User-stored values for address, device operation, and warning and fault levels programmed through the SMBus are preserved while the LM5066I is powered regardless of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared by programing the OPERATION (03h) register with 0h and then 80h.

The SMBus address of the LM5066I is captured based-on the states of the ADR0, ADR1, and ADR2 pins (GND, NC, and VDD) during turn on and is latched into a volatile register after VDD has exceeded its POR threshold of 4.1 V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground. Pulling the VREF pin low also resets the logic and erases the volatile memory of the LM5066I. When released, the VREF pin charges up to its final value and the address is latched into a volatile register when the voltage at the VREF exceeds 2.55 V.

9.5 Programming

9.5.1 PMBus Command Support

The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 2.

Table 2. Supported PMBus Commands

CODE NAME FUNCTION R/W NUMBER OF DATA BYTES DEFAULT VALUE
01h OPERATION Retrieves or stores the operation status R/W 1 80h
03h CLEAR_FAULTS Clears the status registers and re-arms the black box registers for updating Send byte 0
19h CAPABILITY Retrieves the device capability R 1 B0h
43h VOUT_UV_WARN_LIMIT Retrieves or stores output undervoltage warn limit threshold R/W 2 0000h
4Fh OT_FAULT_LIMIT Retrieves or stores over temperature fault limit threshold R/W 2 0FFFh
(256°C)
51h OT_WARN_LIMIT Retrieves or stores over temperature warn limit threshold R/W 2 0FFFh
(256°C)
57h VIN_OV_WARN_LIMIT Retrieves or stores input overvoltage warn limit threshold R/W 2 0FFFh
58h VIN_UV_WARN_LIMIT Retrieves or stores input undervoltage warn limit threshold R/W 2 0000h
5Dh IIN_OC_WARN_LIMIT Retrieves or stores input current warn limit threshold (mirror at D3h) R/W 2 0FFFh
78h STATUS_BYTE Retrieves information about the parts operating status R 1 01h
79h STATUS_WORD Retrieves information about the parts operating status R 2 0801h
7Ah STATUS_VOUT Retrieves information about output voltage status R 1 00h
7Ch STATUS_INPUT Retrieves information about input status R 1 10h
7Dh STATUS_TEMPERATURE Retrieves information about temperature status R 1 00h
7Eh STATUS_CML Retrieves information about communications status R 1 00h
7Fh STATUS_OTHER Retrieves other status information R 1 00h
80h STATUS_MFR_SPECIFIC Retrieves information about circuit breaker and MOSFET shorted status R 1 10h
86h READ_EIN Retrieves energy meter measurement R 6 00h 00h 00h 00h 00h 00h
88h READ_VIN Retrieves input voltage measurement R 2 0000h
89h READ_IIN Retrieves input current measurement (Mirrors at D1h) R 2 0000h
8Bh READ_VOUT Retrieves output voltage measurement R 2 0000h
8Dh READ_TEMPERATURE_1 Retrieves temperature measurement R 2 0190h
97h READ_PIN Retrieves averaged input power measurement (mirror at DFh). R 2 0000h
99h MFR_ID Retrieves manufacturer ID in ASCII characters (TI) R 3 54h
49h
0h
9Ah MFR_MODEL Retrieves part number in ASCII characters. (LM5066I) R 8 4Ch
4Dh
35h
30h
36h
36h
49h
0h
9Bh MFR_REVISION Retrieves part revision letter or number in ASCII (for example, AA) R 2 41h
41h
D0h MFR_SPECIFIC_00
READ_VAUX
Retrieves auxiliary voltage measurement R 2 0000h
D1h MFR_SPECIFIC_01
MFR_READ_IIN
Retrieves input current measurement (Mirror at 89h) R 2 0000h
D2h MFR_SPECIFIC_02
MFR_READ_PIN
Retrieves input power measurement R 2 0000h
D3h MFR_SPECIFIC_03
MFR_IIN_OC_WARN_LIMIT
Retrieves or stores input current limit warn threshold (Mirror at 5Dh) R/W 2 0FFFh
D4h MFR_SPECIFIC_04
MFR_PIN_OP_WARN_LIMIT
Retrieves or stores input power limit warn threshold R/W 2 0FFFh
D5h MFR_SPECIFIC_05
READ_PIN_PEAK
Retrieves measured peak input power measurement R 2 0000h
D6h MFR_SPECIFIC_06
CLEAR_PIN_PEAK
Resets the contents of the peak input power register to 0 Send byte 0
D7h MFR_SPECIFIC_07
GATE_MASK
Allows the user to disable MOSFET gate shutdown for various fault conditions R/W 1 0000h
D8h MFR_SPECIFIC_08
ALERT_MASK
Retrieves or stores user SMBA fault mask R/W 2 FD04h
D9h MFR_SPECIFIC_09
DEVICE_SETUP
Retrieves or stores information about number of retry attempts R/W 1 0000h
DAh MFR_SPECIFIC_10
BLOCK_READ
Retrieves most recent diagnostic and telemetry information in a single transaction R 12 0880h
0000h
0000h
0000h
0000h
0000h
DBh MFR_SPECIFIC_11
SAMPLES_FOR_AVG
Exponent value AVGN for number of samples to be averaged (N = 2AVGN), range = 00h to 0Ch R/W 1 08h
DCh MFR_SPECIFIC_12
READ_AVG_VIN
Retrieves averaged input voltage measurement R 2 0000h
DDh MFR_SPECIFIC_13
READ_AVG_VOUT
Retrieves averaged output voltage measurement R 2 0000h
DEh MFR_SPECIFIC_14
READ_AVG_IIN
Retrieves averaged input current measurement R 2 0000h
DFh MFR_SPECIFIC_15
READ_AVG_PIN
Retrieves averaged input power measurement R 2 0000h
E0h MFR_SPECIFIC_16
BLACK_BOX_READ
Captures diagnostic and telemetry information, which are latched when the first SMBA event occurs after faults are cleared R 12 0880h
0000h
0000h
0000h
0000h
0000h
E1h MFR_SPECIFIC_17
DIAGNOSTIC_WORD_READ
Manufacturer-specific parallel of the STATUS_WORD to convey all FAULT/WARN data in a single transaction R 2 0880h
E2h MFR_SPECIFIC_18
AVG_BLOCK_READ
Retrieves most recent average telemetry and diagnostic information in a single transaction R 12 0880h
0000h
0000h
0000h
0000h
0000h

9.5.2 Standard PMBus Commands

9.5.2.1 OPERATION (01h)

The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command can be used to switch the MOSFET on and off under host control. It is also used to re-enable the MOSFET after a fault triggered shutdown. Writing an OFF command, followed by an ON command, clears all faults and re-enables the device. Writing only an ON after a fault-triggered shutdown does not clear the fault registers or re-enable the device. The OPERATION command is issued with the write byte protocol.

Table 3. Recognized OPERATION Command Values

VALUE MEANING DEFAULT
80h Switch ON 80h
00h Switch OFF N/A

9.5.2.2 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the SMBA signal may not clear or re-asserts almost immediately. Issuing a CLEAR_FAULTS command does not cause the MOSFET to switch back on in the event of a fault turnoff; that must be done by issuing an OPERATION command after the fault condition is cleared. This command uses the PMBus send byte protocol.

9.5.2.3 CAPABILITY (19h)

The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions supported by the LM5066I. This command is read with the PMBus read byte protocol.

Table 4. CAPABILITY Register

VALUE MEANING DEFAULT
B0h Supports packet error check, 400 Kb/s, supports SMBus alert B0h

9.5.2.4 VOUT_UV_WARN_LIMIT (43h)

The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VOUT undervoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VOUT falls below the value in this register, VOUT UV warn flags are set and the SMBA signal is asserted.

Table 5. VOUT_UV_WARN_LIMIT Register

VALUE MEANING DEFAULT
0001h to 0FFFh VOUT undervoltage warning detection threshold 0000h (disabled)
0000h VOUT undervoltage warning disabled N/A

9.5.2.5 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the overtemperature fault detection. Reading and writing to this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched off, OT FAULT flags set, and the SMBA signal asserted. After the measured temperature falls below the value in this register, the MOSFET may be switched back on with the OPERATION command. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature fault detection time is 16 ms.

Table 6. OT_FAULT_LIMIT Register

VALUE MEANING DEFAULT
0000h to 0FFEh Over-temperature fault threshold value 0FFFh (256°C)
0FFFh Over-temperature fault detection disabled N/A

9.5.2.6 OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the over-temperature warning detection. Reading and writing to this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an over-temperature warning is triggered and the OT WARN flags set in the respective registers and the SMBA signal asserted. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature warn detection time is 16 ms.

Table 7. OT_WARN_LIMIT Register

VALUE MEANING DEFAULT
0000h to 0FFEh Over-temperature warn threshold value 0FFFh (256°C)
0FFFh Over-temperature warn detection disabled N/A

9.5.2.7 VIN_OV_WARN_LIMIT (57h)

The VIN_OV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN overvoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN rises above the value in this register, VIN OV warn flags are set in the respective registers and the SMBA signal is asserted.

Table 8. VIN_OV_WARN_LIMIT Register

VALUE MEANING DEFAULT
0h to 0FFEh VIN overvoltage warning detection threshold 0FFFh (disabled)
0FFFh VIN overvoltage warning disabled N/A

9.5.2.8 VIN_UV_WARN_LIMIT (58h)

The VIN_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN undervoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN falls below the value in this register, VIN UV warn flags are set in the respective register, and the SMBA signal is asserted.

Table 9. VIN_UV_WARN_LIMIT Register

VALUE MEANING DEFAULT
1h to 0FFFh VIN undervoltage warning detection threshold 0000h (disabled)
0000h VIN undervoltage warning disabled N/A

9.5.2.9 STATUS_BYTE (78h)

The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5066I. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued.

Table 10. STATUS_BYTE Definitions

BIT NAME MEANING DEFAULT
7 BUSY Not supported, always 0 0
6 OFF This bit is asserted if the MOSFET is not switched on for any reason. 0
5 VOUT OV Not supported, always 0 0
4 IOUT OC Not supported, always 0 0
3 VIN UV fault A VIN undervoltage fault has occurred 0
2 TEMPERATURE A temperature fault or warning has occurred 0
1 CML A communication fault has occurred 0
0 None of the above A fault or warning not listed in bits [7:1] has occurred 1

9.5.2.10 STATUS_WORD (79h)

The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5066I. Accesses to this command should use the PMBus read word protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR _FAULTS command issued. The INPUT and VIN UV flags default to 1 on startup; however, they are cleared to 0 after the first time the input voltage exceeds the resistor-programmed UVLO threshold.

Table 11. STATUS_WORD Definitions

BIT NAME MEANING DEFAULT
15 VOUT An output voltage fault or warning has occurred 0
14 IOUT/POUT Not supported, always 0 0
13 INPUT An input voltage or current fault has occurred 0
12 FET FAIL FET is shorted 0
11 POWER GOOD The Power Good signal has been negated 1
10 FANS Not supported, always 0 0
9 CB_Fault Circuit breaker fault triggered 0
8 UNKNOWN Not supported, always 0 0
7 BUSY Not supported, always 0 0
6 OFF This bit is asserted if the MOSFET is not switched on for any reason. 0
5 VOUT OV Not supported, always 0 0
4 IOUT OC Not supported, always 0 0
3 VIN UV A VIN undervoltage fault has occurred 0
2 TEMPERATURE A temperature fault or warning has occurred 0
1 CML A communication fault has occurred 0
0 None of the above A fault or warning not listed in bits [7:1] has occurred 1

9.5.2.11 STATUS_VOUT (7Ah)

The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV warn flag. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued.

Table 12. STATUS_VOUT Definitions

BIT NAME MEANING DEFAULT
7 VOUT OV fault Not supported, always 0 0
6 VOUT OV warn Not supported, always 0 0
5 VOUT UV warn A VOUT undervoltage warning has occurred 0
4 VOUT UV fault Not supported, always 0 0
3 VOUT max Not supported, always 0 0
2 TON max fault Not supported, always 0 0
1 TOFF max fault Not supported, always 0 0
0 VOUT tracking error Not supported, always 0 0

9.5.2.12 STATUS_INPUT (7Ch)

The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags related to input voltage, current, and power. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. The VIN UV warn flag defaults to 1 on startup; however, it is cleared to 0 after the first time the input voltage increases above the resistor-programmed UVLO threshold.

Table 13. STATUS_INPUT Definitions

BIT NAME MEANING DEFAULT
7 VIN OV fault A VIN overvoltage fault has occurred 0
6 VIN OV warn A VIN overvoltage warning has occurred 0
5 VIN UV warn A VIN undervoltage warning has occurred 1
4 VIN UV fault A VIN undervoltage fault has occurred 0
3 Insufficient voltage Not supported, always 0 0
2 IIN OC fault An IIN overcurrent fault has occurred 0
1 IIN OC warn An IIN overcurrent warning has occurred 0
0 PIN OP warn A PIN overpower warning has occurred 0

9.5.2.13 STATUS_TEMPERATURE (7dh)

The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags related to the temperature telemetry value. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued.

Table 14. STATUS_TEMPERATURE Definitions

BIT NAME MEANING DEFAULT
7 Overtemp fault An overtemperature fault has occurred 0
6 Overtemp warn An overtemperature warning has occurred 0
5 Undertemp warn Not supported, always 0 0
4 Undertemp fault Not supported, always 0 0
3 Reserved Not supported, always 0 0
2 Reserved Not supported, always 0 0
1 Reserved Not supported, always 0 0
0 Reserved Not supported, always 0 0

9.5.2.14 STATUS_CML (7Eh)

The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to communication faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, a CLEAR_FAULTS command should be issued.

Table 15. STATUS_CML Definitions

BIT NAME DEFAULT
7 Invalid or unsupported command received 0
6 Invalid or unsupported data received 0
5 Packet error check failed 0
4 Not supported, always 0 0
3 Not supported, always 0 0
2 Reserved, always 0 0
1 Miscellaneous communications fault has occurred 0
0 Not supported, always 0 0

9.5.2.15 STATUS_OTHER (7Fh)

Table 16. STATUS_OTHER Definitions

BIT NAME DEFAULT
7 Reserved: Always 0 0
6 Reserved: Always 0 0
5 CB Fault 0
4 Not supported, always 0 0
3 Not supported, always 0 0
2 Not supported, always 0 0
1 Not supported, always 0 0
0 Not supported, always 0 0

9.5.2.16 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific status information. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued.

Table 17. STATUS_MFR_SPECIFIC Definitions

BIT MEANING DEFAULT
7 Circuit breaker fault 0
6 External MOSFET shorted fault 0
5 Not supported, always 0 0
4 Defaults loaded 1
3 Not supported, always 0 0
2 Not supported, always 0 0
1 Not supported, always 0 0
0 Not supported, always 0 0

9.5.2.17 READ_EIN (86h)

The READ_EIN command is a standard PMBus command that returns information the host can use to calculate average input power consumption. Accesses to this command should use the PMBus block read protocol. The information provided by this command is independent of any device-specific averaging period. Six data bytes are returned by this command. The first two bytes are the two's complement signed output of an accumulator that continuously sums samples of the instantaneous input power. The accumulator value is the summation of the instantaneous power measurement. These two data bytes are formatted in the DIRECT format. The next data byte is a rollover count for the accumulator. This byte is an unsigned integer that indicates the number of times the accumulator has rolled over from its maximum positive unsigned integer (7FFFh) to 0. The last three data bytes are a 24-bit unsigned integer that counts the number of samples of the instantaneous input power. This value also rolls over periodically from its maximum positive value to 0. It is up to the host to keep track of the sample count and account for the rollovers.

The combination of the accumulator and the roller count may overflow after a period of several seconds. Similarly, the sample count value overflows, but this event only occurs once every few hours.

To convert the data obtained from two separate READ_EIN commands into average power, first convert the accumulator and rollover count to an unsigned integer (see Equation 1).

Equation 1. Accumulator_23 = (rollover_count << 15) + accumulator

Note that the overflow of this variable needs to be monitored and properly accounted for. Data from the previous calculation, along with the sample count values from the corresponding register access, can be used to get the unscaled average power:

Equation 2. Eq_READ_IN_86h_SNVS950.gif

where

  • Accumulator_23 [n] = Overflow corrected, 23-bit accumulator data from this read
  • Sample_count [n] = Sample count data from this read
  • Accumulator_23 [n – 1] = Overflow corrected, 23-bit accumulator data from previous read
  • Sample_count [n – 1] = Sample count data from previous read
  • Unscaled average power is now in the same units as the data from the READ_PIN command. Coefficients from Table 47 are used to convert the unscaled average power to Watts.

Table 18. READ_EIN Definition

BYTE MEANING DEFAULT
0 Number of bytes 6
1 Power accumulator low byte 0
2 Power accumulator high byte 0
3 Power accumulator rollover count 0
4 Sample count low byte 0
5 Sample count mid byte 0
6 Sample count high byte 0

9.5.2.18 READ_VIN (88h)

The READ_VIN command is a0 standard PMBus command that returns the 12-bit measured value of the input voltage. Reading this register should use the coefficients shown in Table 47. Accesses to this command should use the P0MBus read word protocol. This value is also used internally for the VIN overvoltage and undervoltage warning detection.

Table 19. 0READ_VIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured va0lue for VIN 0000h

9.5.2.19 READ_IIN (89h)

The READ_IIN command is a standard PMBus command that returns the 12-bit measured value of the input current. Reading this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read word protocol. This value is also mirrored at (D1h).

Table 20. READ_IIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for IIN 0000h

9.5.2.20 READ_VOUT (8Bh)

The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the output voltage. Reading this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VOUT undervoltage warning detection.

Table 21. READ_VOUT Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for VOUT 0000h

9.5.2.21 READ_TEMPERATURE_1 (8Dh)

The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of the temperature measured by the external temperature sense diode. Reading this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the overtemperature fault and warning detection. This data has a range of –256°C to 255°C after the coefficients are applied.

Table 22. READ_TEMPERATURE_1 Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for TEMPERATURE 0000h

9.5.2.22 READ_PIN (97h)

The READ_PIN command is a standard PMBus command that returns the 12-bit measured value of the input power. Reading this register should use the coefficients shown in Table 47. Accesses to this command should use the PMBus read word protocol. This value is also mirrored at (D5h).

Table 23. READ_PIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for PIN 0000h

9.5.2.23 MFR_ID (99h)

The MFR_ID command is a standard PMBus command that returns the identification of the manufacturer. To read the MFR_ID, use the PMBus block read protocol.

Table 24. MFR_ID Register

BYTE NAME VALUE
0 Number of bytes 03h
1 MFR ID-1 54h ‘T’
2 MFR ID-2 29h ‘I’
3 MFR ID-3 00h

9.5.2.24 MFR_MODEL (9Ah)

The MFR_MODEL command is a standard PMBus command that returns the part number of the chip. To read the MFR_MODEL, use the PMBus block read protocol.

Table 25. MFR_MODEL Register

BYTE NAME VALUE
0 Number of bytes 08h
1 MFR ID-1 4Ch ‘L’
2 MFR ID-2 4Dh ‘M’
3 MFR ID-3 35h ‘5’
4 MFR ID-4 30h ‘0’
5 MFR ID-5 36h ‘6’
6 MFR ID-6 36h ‘6’
7 MFR ID-7 49h 'I'
8 MFR ID-8 00h

9.5.2.25 MFR_REVISION (9Bh)

The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To read the MFR_REVISION, use the PMBus block read protocol.

Table 26. MFR_REVISION Register

BYTE NAME VALUE
0 Number of bytes 02h
1 MFR ID-1 41h ‘A’
2 MFR ID-2 41h ‘A’

9.5.3 Manufacturer Specific PMBus Commands

9.5.3.1 MFR_SPECIFIC_00: READ_VAUX (D0h)

The READ_VAUX command reports the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to 2.97 V to ground are reported at plus full scale (0FFFh). Voltages less than or equal to 0 V referenced to ground are reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus read word protocol.

Table 27. READ_VAUX Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for VAUX input 0000h

9.5.3.2 MFR_SPECIFIC_01: MFR_READ_IIN (D1h)

The MFR_READ_IIN command reports the 12-bit ADC measured current sense voltage. To read data from the MFR_READ_IIN command, use the PMBus read word protocol. Reading this register should use the coefficients shown in Table 47. See the section Reading and Writing Telemetry Data and Warning Thresholds to calculate the values to use.

Table 28. MFR_READ_IIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Measured value for input current sense voltage 0000h

9.5.3.3 MFR_SPECIFIC_02: MFR_READ_PIN (D2h)

The MFR_READ_PIN command reports the upper 12 bits of the VIN × IIN product as measured by the 12-bit ADC. To read data from the MFR_READ_PIN command, use the PMBus read word protocol. Reading this register should use the coefficients shown in Table 47. See the section Reading and Writing Telemetry Data and Warning Thresholds to calculate the values to use.

Table 29. MFR_READ_PIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh VALUE for input current x input voltage 0000h

9.5.3.4 MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)

The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input overcurrent warning threshold. In the event that the input current rises above the value set in this register, the IIN overcurrent flags are set in the respective registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus read/write word protocol. Reading and writing to this register should use the coefficients shown in Table 47.

Table 30. MFR_IIN_OC_WARN_LIMIT Register

VALUE MEANING DEFAULT
0000h to 0FFEh Value for input overcurrent warn limit 0FFFh
0FFFh Input overcurrent warning disabled N/A

9.5.3.5 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)

The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN over-power flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus read/write word protocol. Reading and writing to this register should use the coefficients shown in Table 47.

Table 31. MFR_PIN_OPWARN_LIMIT Register

VALUE MEANING DEFAULT
0000h to 0FFEh Value for input over power warn limit 0FFFh
0FFFh Input over power warning disabled N/A

9.5.3.6 MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)

The READ_PIN_PEAK command reports the maximum input power measured since a power-on reset or the last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus read word protocol. Use the coefficients shown in Table 47.

Table 32. READ_PIN_PEAK Register

VALUE MEANING DEFAULT
0000h to 0FFFh Maximum value for input current × input voltage since reset or last clear 0000h

9.5.3.7 MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)

The CLEAR_PIN_PEAK command clears the PIN PEAK register. This command uses the PMBus send byte protocol.

9.5.3.8 MFR_SPECIFIC_07: GATE_MASK (D7h)

The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers are still updated (STATUS, DIAGNOSTIC) and SMBA is still asserted. This register is accessed with the PMBus read/write byte protocol.

CAUTION

Inhibiting the MOSFET switch off in response to overcurrent or circuit breaker fault conditions will likely result in the destruction of the MOSFET. This functionality must be used with great care and supervision.

Table 33. MFR_SPECIFIC_07 Gate Mask Definitions

BIT NAME DEFAULT
7 Not used, always 0 0
6 Not used, always 0 0
5 VIN UV FAULT 0
4 VIN OV FAULT 0
3 IIN/PFET FAULT 0
2 OVERTEMP FAULT 0
1 Not used, always 0 0
0 CIRCUIT BREAKER FAULT 0

The IIN/PFET fault refers to the input current fault and the MOSFET power dissipation fault. There is no input power fault detection, only input power warning detection.

9.5.3.9 MFR_SPECIFIC_08: ALERT_MASK (D8h)

The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an SMBA being asserted. When the corresponding bit is high, that condition does not cause the SMBA to be asserted. If that condition occurs, the registers where that condition is captured is still updated (STATUS registers, DIAGNOSTIC_WORD) and the external MOSFET gate control is still active (VIN_OV_FAULT, VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus read/write word protocol. The VIN UNDERVOLTAGE FAULT flag defaults to 1 on startup; however, it clears to 0 after the first time the input voltage increases above the resistor-programmed UVLO threshold.

Table 34. ALERT_MASK Definitions

BIT NAME DEFAULT
15 VOUT UNDERVOLTAGE WARN 1
14 IIN LIMIT warn 1
13 VIN UNDERVOLTAGE WARN 1
12 VIN OVERVOLTAGE WARN 1
11 POWER GOOD 1
10 OVERTEMP WARN 1
9 Not used 0
8 OVERPOWER LIMIT WARN 1
7 Not used 0
6 EXT_MOSFET_SHORTED 0
5 VIN UNDERVOLTAGE FAULT 1
4 VIN OVERVOLTAGE FAULT 0
3 IIN/PFET FAULT 0
2 OVERTEMPERATURE FAULT 0
1 CML FAULT (communications fault) 0
0 CIRCUIT BREAKER FAULT 0

9.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)

The DEVICE_SETUP command can be used to override pin settings to define operation of the LM5066I under host control. This command is accessed with the PMBus read/write byte protocol.

Table 35. DEVICE_SETUP Byte Format

BIT NAME MEANING
7:5 Retry setting 111 = Unlimited retries
110 = Retry 16 times
101 = Retry 8 times
100 = Retry 4 times
011 = Retry 2 times
010 = Retry 1 time
001 = No retries
000 = Pin configured retries
4 Current limit setting 0 = High setting (50 mV)
1 = Low setting (26 mV)
3 CB/CL ratio 0 = Low setting (1.9x)
1 = High setting (3.9x)
2 Current limit configuration 0 = Use pin settings
1 = Use SMBus settings
1 Unused
0 Unused

To configure the current limit setting with this register, it is necessary to set the current limit configuration bit (2) to 1 to enable the register to control the current limit function and the current limit setting bit (4) to select the desired setting. If the current limit configuration bit is not set, the pin setting is used. The circuit breaker to current limit ratio value is set by the CB / CL ratio bit (3). Note that if the current limit configuration is changed, the samples for the telemetry averaging function are not reset. TI recommends to allow a full averaging update period with the new current limit configuration before processing the averaged data.

Note that the current limit configuration affects the coefficients used for the current and power measurements and warning registers.

9.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)

The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the LM5066I in a single SMBus transaction. The block is 12-bytes long with telemetry information being sent out in the same manner as if an individual READ_XXX command had been issued (shown in Table 36). The contents of the block read register are updated every clock cycle (85 ns) as long as the SMBus interface is idle. BLOCK_READ also specifies that the VIN, VOUT, IIN and PIN measurements are all time-aligned. If separate commands are used, individual samples may not be time-aligned because of the delay necessary for the communication protocol.

The block read command is read through the PMBus block read protocol.

Table 36. BLOCK_READ Register Format

Byte Count (Always 12) (1 Byte)
DIAGNOSTIC_WORD (1 word)
IIN_BLOCK (1 word)
VOUT_BLOCK (1 word)
VIN_BLOCK (1 word)
PIN_BLOCK (1 word)
TEMP_BLOCK (1 word)

9.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)

The SAMPLES_FOR_AVG command is a manufacturer-specific command for setting the number of samples used in computing the average values for IIN, VIN, VOUT, and PIN. The decimal equivalent of the AVGN nibble is the power of 2 samples, (for example, AVGN = 12 equates to N = 4096 samples used in computing the average). The LM5066I supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096. The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, and PIN simultaneously. The LM5066I uses simple averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by the number of samples. Averaging is calculated according to the following sequence:

Equation 3. Y = (X(N) + X(N-1) + ... + X(0)) / N

When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a whole new sequence begins that requires the same number of samples (in this example, 4096) to be taken before the new average is ready.

Table 37. SAMPLES_FOR_AVG Register

AVGN (b) N = 2AVGN Averaging / Register Update Period (ms)
0000b 1 1
0001b 2 2
0010b 4 4
0011b 8 8
0100b 16 16
0101b 32 32
0110b 64 64
0111b 128 128
1000b 256 256
1001b 512 512
1010b 1024 1024
1011b 2048 2048
1100b 4096 4096

Note that a change in the SAMPLES_FOR_AVG register is not reflected in the average telemetry measurements until the present averaging interval has completed. The default setting for AVGN is 1000b, or 08h.

The SAMPLES_FOR_AVG register is accessed with the PMBus read/write byte protocol.

Table 38. SAMPLES_FOR_AVG Register

VALUE MEANING DEFAULT
00h to 0Ch Exponent (AVGN) for number of samples to average over 00h

9.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)

The READ_AVG_VIN command reports the 12-bit ADC measured input average voltage. If the data is not ready, the returned value is the previous averaged data. However, if there is no previously averaged data, the default value (0000h) is returned. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 47.

Table 39. READ_AVG_VIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Average of measured values for input voltage 0000h

9.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)

The READ_AVG_VOUT command reports the 12-bit ADC measured current sense average voltage. The returned value is the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 47.

Table 40. READ_AVG_VOUT Register

VALUE MEANING DEFAULT
0000h to 0FFFh Average of measured values for output voltage 0000h

9.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)

The READ_AVG_IIN command reports the 12-bit ADC measured current sense average voltage. The returned value is the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 47.

Table 41. READ_AVG_IIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Average of measured values for current sense voltage 0000h

9.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)

The READ_AVG_PIN command reports the 12-bit ADC measured VIN x IIN product. The returned value is the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 47.

Table 42. READ_AVG_IIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Average of measured values for current sense voltage 0000h

9.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN

The READ_AVG_PIN command reports the upper 12-bits of the average VIN × IIN product as measured by the 12-bit ADC. The user can read the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 47.

Table 43. READ_AVG_PIN Register

VALUE MEANING DEFAULT
0000h to 0FFFh Average of measured value for input voltage x input current sense voltage 0000h

9.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)

The BLACK BOX READ command retrieves the BLOCK READ data which was latched in at the first assertion of SMBA by the LM5066I. It is re-armed with the CLEAR_FAULTS command. It is the same format as the BLOCK_READ registers, the only difference is that its contents are updated with the SMBA edge rather than the internal clock edge. This command is read with the PMBus block read protocol.

9.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)

The READ_DIAGNOSTIC_WORD PMBus command reports all of the LM5066I faults and warnings in a single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD register. The READ_DIAGNOSTIC_WORD command should be read with the PMBus read word protocol. The READ_DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and AVG_BLOCK_READ operations. Note that if UVLO is pulled low to shutt OFF the FET, the diagnostic word will return 08E0h.

Table 44. DIAGNOSTIC_WORD Format

BIT MEANING DEFAULT
15 VOUT_UNDERVOLTAGE_WARN 0
14 IIN_OP_WARN 0
13 VIN_UNDERVOLTAGE_WARN 0
12 VIN_OVERVOLTAGE_WARN 0
11 POWER GOOD 1
10 OVER_TEMPERATURE_WARN 0
9 TIMER_LATCHED_OFF 0
8 EXT_MOSFET_SHORTED 0
7 CONFIG_PRESET 1
6 DEVICE_OFF 0
5 VIN_UNDERVOLTAGE_FAULT 0
4 VIN_OVERVOLTAGE_FAULT 0
3 IIN_OC/PFET_OP_FAULT 0
2 OVER_TEMPERATURE_FAULT 0
1 CML_FAULT 0
0 CIRCUIT_BREAKER_FAULT 0

9.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)

The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, and PIN) and temperature to capture all of the operating information of the part in a single PMBus transaction. The block is 12-bytes long with telemetry information sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown in Table 45). AVG_BLOCK_READ also specifies that the VIN, VOUT, and IIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ command, use the SMBus block read protocol.

Table 45. AVG_BLOCK_READ Register Format

Byte Count (Always 12) (1 Byte)
DIAGNOSTIC_WORD (1 word)
AVG_IIN (1 word)
AVG_VOUT (1 word)
AVG_VIN (1 word)
AVG_PIN (1 word)
TEMPERATURE (1 word)
301159a2.gifFigure 17. Command / Register and Alert Flow Diagram

9.5.4 Reading and Writing Telemetry Data and Warning Thresholds

All measured telemetry data and user-programmed warning thresholds are communicated in 12-bit two’s complement binary numbers read or written in 2-byte increments conforming to the direct format as described in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II). The organization of the bits in the telemetry or warning word is shown in Table 46, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the temperature word ranges from 0 to 65535.

Table 46. Telemetry and Warning Word Format

Byte B7 B6 B5 B4 B3 B2 B1 B0
1 Bit_7 Bit_6 Bit_5 Bit_4 Bit_3 Bit_2 Bit_1 Bit_0
2 0 0 0 0 Bit_11 Bit_10 Bit_9 Bit_8

Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the values received into a reading of volts, amperes, watts, or other units using the following relationship:

Equation 4. Eq03_x_snvs950.gif

where

  • X = The calculated real-world value (volts, amps, watt, and so forth)
  • m = The slope coefficient
  • Y = A 2-byte two's complement integer received from device
  • b = The offset, a 2-byte two's complement integer
  • R = The exponent, a 1-byte two's complement integer

R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy.

Table 47. Telemetry and Warning Conversion Coefficients

Commands Condition Format Number of Data Bytes m b R Unit
READ_VIN, READ_AVG_VIN
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
DIRECT 2 4617 –140.0 –2 V
READ_VOUT, READ_AVG_VOUT
VOUT_UV_WARN_LIMIT
DIRECT 2 4602 500.0 –2 V
READ_VAUX DIRECT 2 13774 73.0 –1 V
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
CL = VDD DIRECT 2 15076 -503.9 –2 A
READ_IN, READ_AVG_IN(1)
MFR_IIN_OC_WARN_LIMIT
CL = GND DIRECT 2 7645 100 –2 A
READ_PIN, READ_AVG_PIN(1), READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = VDD DIRECT 2 1701 –4000 –3 W
READ_PIN, READ_AVG_PIN(1), READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = GND DIRECT 2 860.6 –965 –3 W
READ_TEMPERATURE_1
OT_WARN_LIMIT
OT_FAULT_LIMIT
DIRECT 2 16000 0 –3 °C
(1) The coefficients relating to current/power measurements and warning thresholds shown are normalized to a sense resistor (RS) value of 1 mΩ. In general, the current or power coefficients can be calculated using the relationships shown in Table 48.

Table 48. Current and Power Telemetry and Warning Conversion Coefficients (RS in mΩ)

Commands Condition Format Number of Data Bytes m b R Unit
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
CL = VDD DIRECT 2 15076 × RS –503.9 –2 A
READ_IIN, READ_AVG_IIN(1)
MFR_IIN_OC_WARN_LIMIT
CL = GND DIRECT 2 7645 × RS 100.0 –2 A
READ_PIN, READ_AVG_PIN(1), READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = VDD DIRECT 2 1701 × RS –4000 –3 W
READ_PIN, READ_AVG_PIN(1), READ_PIN_PEAK
MFR_PIN_OP_WARN_LIMIT
CL = GND DIRECT 2 860.6 × RS –965.0 –3 W

Take care to adjust the exponent coefficient, R, such that the value of m remains within the range of –32768 to 32767. For example, if a 5-mΩ sense resistor is used, the correct coefficients for the READ_IIN command with CL = VDD would be m = 7553, b = –65, R = –1.

9.5.5 Determining Telemetry Coefficients Empirically With Linear Fit

The coefficients for telemetry measurements and warning thresholds presented in Table 47 are adequate for the majority of applications. Current and power coefficients are dependent on RSNS and must be calculated per application. Table 48 provides the equations necessary for calculating the current and power coefficients for the general case. These were obtained by characterizing multiple units over temperature and are considered optimal. The small signal nature of the current and power measurement makes it more susceptible to PCB parasitics than other telemetry channels. In addition there is some variation in RSNS and the LM5066I itself. This may cause slight variations in the optimum coefficients (m, b, and R) for converting from digital values to real world values (for example, amps and watts). To maximize telemetry accuracy, the coefficients can be calibrated for a given board using empirical methods. This would determine optimum coefficients to cancel out the error from PCB parasitics, RSNS variation, and the variation of LM5066I. It is not considered good practice to take measurements on one board and use the computed coefficients for all units in production, because the RSNS and the LM5066I on a given board are randomly chosen and do not represent a statistical mean. It is recommended to either calibrate all boards individually or to use the recommended coefficients from Table 48.

The optimal current coefficients for a specific board can be determined using the following method:

  1. While the LM5066I is in normal operation, measure the voltage across the sense resistor using Kelvin test points and a high accuracy DVM while controlling the load current. Record the integer value returned by the READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should span nearly the full-scale range of the current (for example, voltage across RSNS of 5 and 20 mV).
  2. Convert the measured voltages to currents by dividing them by the value of RSNS. For best accuracy, the value of RSNS should be measured. Table 49 assumes a sense resistor value of 5 mΩ.
  3. Table 49. Measurements for Linear Fit Determination of Current Coefficients

    Measured Voltage Across
    RS (V)
    Measured Current
    (A)
    READ_AVG_IIN
    (Integer Value)
    0.005 1 568
    0.01 2 1108
    0.02 4 2185
  4. Using the spreadsheet (or a math program) determine the slope and the y-intercept of the data returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 47:
    • READ_AVG_IN value = slope × (Measured Current) + (y-intercept)
    • Slope = 538.9
    • Y-intercept = 29.5
  5. To determine the m coefficient, simply shift the decimal point of the calculated slope to arrive at integer with a suitable number of significant digits for accuracy (typically 4) while staying with the range of –32768 to 32767. This shift in the decimal point equates to the R coefficient. For the slope value shown in the previous step, the decimal point would be shifted to the right once hence R = –1.
  6. After the R coefficient has been determined, the b coefficient is found by multiplying the y-intercept by  10 –R. In this case the value of b = 295.
    • Calculated current coefficients:
    • m = 5389
    • b = 295
    • R = –1
Equation 5. Eq04_-R_snva950.gif

where

  • X = The calculated real-world value (volts, amps, watts, temperature)
  • m = The slope coefficient, is the 2-byte, two's complement integer
  • Y = A 2-byte two's complement integer received from device
  • b = The offset, a 2-byte two's complement integer
  • R = The exponent, a 1-byte two's complement integer

This procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting measured current for some other parameter (for example, power or voltage).

9.5.6 Writing Telemetry Data

There are several locations that require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using this method as prescribed by the PMBus revision section 7.2.2 Sending a Value

Equation 6. Eq05_Y_snva950.gif

where

  • X = The calculated real-world value (volts, amps, watts, temperature)
  • m = The slope coefficient is the 2-byte, two's complement integer
  • Y = A 2-byte two's complement integer received from device
  • b = The offset, a 2-byte two's complement integer
  • R = The exponent, a 1-byte two's complement integer

9.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)

The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27 addresses for communicating with the LM5066I. Table 50 depicts 7-bit addresses (eighth bit is read/write bit).

Table 50. Device Addressing

ADR2 ADR1 ADR0 DECODED ADDRESS
Z Z Z 40h
Z Z 0 41h
Z Z 1 42h
Z 0 Z 43h
Z 0 0 44h
Z 0 1 45h
Z 1 Z 46h
Z 1 0 47h
Z 1 1 10h
0 Z Z 11h
0 Z 0 12h
0 Z 1 13h
0 0 Z 14h
0 0 0 15h
0 0 1 16h
0 1 Z 17h
0 1 0 50h
0 1 1 51h
1 Z Z 52h
1 Z 0 53h
1 Z 1 54h
1 0 Z 55h
1 0 0 56h
1 0 1 57h
1 1 Z 58h
1 1 0 59h
1 1 1 5Ah

9.5.8 SMBA Response

The SMBA effectively has two masks:

  • The alert mask register at D8h
  • The ARA automatic mask.

The ARA automatic mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that this part was the one that returned its address. When a part responds to the ARA read, it releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its address, the SMBA signal de-asserts.

The way that the LM5066I releases the SMBA signal is by setting the ARA automatic mask bit for all fault conditions present at the time of the ARA read. All status registers will still the fault condition, but it does not generate a SMBA on that fault again until the ARA automatic mask is cleared by the host issuing a CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the ARA read is not done. Figure 18 depicts a schematic version of this flow.

301159a0.gifFigure 18. Typical Flow Schematic for SMBA Fault