SNVS497F November   2008  – September 2016 LM27341 , LM27341-Q1 , LM27342 , LM27342-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Function
      2. 7.3.2 Low Input Voltage Considerations
      3. 7.3.3 High Output Voltage Considerations
      4. 7.3.4 Frequency Synchronization
      5. 7.3.5 Current Limit
      6. 7.3.6 Frequency Foldback
      7. 7.3.7 Output Overvoltage Protection
      8. 7.3.8 Undervoltage Lockout
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Pin and Shutdown Mode
      2. 7.4.2 Soft-Start Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Inductor Selection
        1. 8.1.1.1 Inductor Calculation Example
      2. 8.1.2  Inductor Material Selection
      3. 8.1.3  Input Capacitor
      4. 8.1.4  Output Capacitor
      5. 8.1.5  Catch Diode
      6. 8.1.6  Boost Diode (Optional)
      7. 8.1.7  Boost Capacitor
      8. 8.1.8  Output Voltage
      9. 8.1.9  Feedforward Capacitor (Optional)
      10. 8.1.10 Calculating Efficiency and Junction Temperature
        1. 8.1.10.1 Schottky Diode Conduction Losses
        2. 8.1.10.2 Inductor Conduction Losses
        3. 8.1.10.3 MOSFET Conduction Losses
        4. 8.1.10.4 MOSFET Switching Losses
        5. 8.1.10.5 IC Quiescent Losses
        6. 8.1.10.6 MOSFET Driver Losses
        7. 8.1.10.7 Total Power Losses
        8. 8.1.10.8 Efficiency Calculation Example
        9. 8.1.10.9 Calculating Junction Temperature
          1. 8.1.10.9.1 Conduction
          2. 8.1.10.9.2 Convection
          3. 8.1.10.9.3 Method 1
          4. 8.1.10.9.4 Method 2
            1. 8.1.10.9.4.1 Method 2 Example
          5. 8.1.10.9.5 Method 3
            1. 8.1.10.9.5.1 Method 3 Example
    2. 8.2 Typical Applications
      1. 8.2.1 LM2734x Configuration From VIN = 7 V to 16 V, VOUT = 5 V For Full Load at 2 MHz
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LM2734x Configuration From VIN = 7 V to 16 V, VOUT = 5 V For Full Load at 1 MHz
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 LM2734x Configuration From VIN = 5 V to 16 V, VOUT = 3.3 V For Full Load at 2 MHz
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 LM2734x Configuration From VIN = 5 V to 16 V, VOUT = 3.3 V For Full Load at 2 MHz With SYNC = GND
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
      5. 8.2.5 LM2734x Configuration From VIN = 5 V to 16 V, VOUT = 3.3 V For Full Load at 2 MHz With SYNC = 1 MHz
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
        3. 8.2.5.3 Application Curves
      6. 8.2.6 LM2734x Configuration From VIN = 3.3 V to 16 V, VOUT = 1.8 V For Full Load at 2 MHz With SYNC = 1 GND
        1. 8.2.6.1 Design Requirements
        2. 8.2.6.2 Detailed Design Procedure
        3. 8.2.6.3 Application Curves
      7. 8.2.7 LM2734x Configuration From VIN = 3.3 V to 16 V, VOUT = 1.8 V For Full Load at 2 MHz With SYNC = 1 MHz
        1. 8.2.7.1 Design Requirements
        2. 8.2.7.2 Detailed Design Procedure
        3. 8.2.7.3 Application Curves
      8. 8.2.8 LM2734x Configuration From VIN = 3.3 V to 9 V, VOUT = 1.2 V For Full Load at 2 MHz With SYNC = 2 MHz
        1. 8.2.8.1 Design Requirements
        2. 8.2.8.2 Detailed Design Procedure
        3. 8.2.8.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout
      2. 10.1.2 Ground Plane and Shape Routing
      3. 10.1.3 FB Loop
      4. 10.1.4 PCB Summary
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

10.1.1 Compact Layout

The performance of any switching converter depends as much upon the layout of the PCB as the component selection. The following guidelines help the user design a circuit with maximum rejection of outside EMI and minimum generation of unwanted EMI.

Parasitic inductance can be reduced by keeping the power path components close together and keeping the area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In particular, the switch node (where L1, D1, and the SW pin connect) must be just large enough to connect all three components without excessive heating from the current it carries. The LM2734x and LM2734x-Q1 operate in two distinct cycles (see Figure 27) whose high current paths are shown in Figure 58.

LM27341 LM27342 LM27341-Q1 LM27342-Q1 30005660.gif Figure 58. Buck Converter Current Loops

The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time.

10.1.2 Ground Plane and Shape Routing

The diagram of Figure 58 is also useful for analyzing the flow of continuous current versus the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing must be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just like any other circuit path. The path between the input source and the input capacitor and the path between the catch diode and the load are examples of continuous current paths. In contrast, the path between the catch diode and the input capacitor carries a large pulsating current. This path must be routed with a short, thick shape, preferably on the component side of the PCB. Multiple vias in parallel must be used right at the pad of the input capacitor to connect the component side shapes to the ground plane. A second pulsating current loop that is often ignored is the gate drive loop formed by the SW and BOOST pins and boost capacitor CBOOST. To minimize this loop and the EMI it generates, keep CBOOST close to the SW and BOOST pins.

10.1.3 FB Loop

The FB pin is a high-impedance input, and the loop created by R2, the FB pin and ground must be made as small as possible to maximize noise rejection. R2 must therefore be placed as close as possible to the FB and GND pins of the IC.

10.1.4 PCB Summary

  1. Minimize the parasitic inductance by keeping the power path components close together and keeping the area of the high-current loops small.
  2. The most important consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground connections must be immediately adjacent, with multiple vias in parallel at the pad of the input capacitor connected to GND. Place CIN and D1 as close to the IC as possible.
  3. Next in importance is the location of the GND connection of the COUT capacitor, which must be near the GND connections of CIN and D1.
  4. There must be a continuous ground plane on the copper layer directly beneath the converter. This reduces parasitic inductance and EMI.
  5. The FB pin is a high impedance node and care must be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors must be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 must be routed away from the inductor and any other traces that are switching.
  6. High AC currents flow through the VIN, SW and VOUT traces, so they must be as short and wide as possible. However, making the traces wide increases radiated noise, so the layout designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor.

The remaining components must also be placed as close as possible to the IC. See AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054) for further considerations and the LM27342 demo board as an example of a four-layer layout.

10.2 Layout Example

LM27341 LM27342 LM27341-Q1 LM27342-Q1 Layout_Ex_SNVS497.gif Figure 59. Top Layer and Overlay