ZHCS573I August   2010  – April 2018 LM25119

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      典型应用电路
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-Up Regulator
      2. 7.3.2  UVLO
      3. 7.3.3  Enable 2
      4. 7.3.4  Oscillator and Sync Capability
      5. 7.3.5  Error Amplifiers and PWM Comparators
      6. 7.3.6  Ramp Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  Hiccup Mode Current Limiting
      9. 7.3.9  Soft Start
      10. 7.3.10 HO and LO Output Drivers
      11. 7.3.11 Maximum Duty Cycle
      12. 7.3.12 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Diode Emulation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Miscellaneous Functions
      2. 8.1.2 Interleaved Two-Phase Operation
      3. 8.1.3 Interleaved 4-Phase Operation
    2. 8.2 Typical Applications
      1. 8.2.1 Dual-output Design Example
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 External Components
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Timing Resistor
          2. 8.2.1.2.2  Output Inductor
          3. 8.2.1.2.3  Current Sense Resistor
          4. 8.2.1.2.4  Ramp Resistor and Ramp Capacitor
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Input Capacitors
          7. 8.2.1.2.7  VCC Capacitor
          8. 8.2.1.2.8  Bootstrap Capacitor
          9. 8.2.1.2.9  Soft Start Capacitor
          10. 8.2.1.2.10 Restart Capacitor
          11. 8.2.1.2.11 Output Voltage Divider
          12. 8.2.1.2.12 UVLO Divider
          13. 8.2.1.2.13 MOSFET Selection
          14. 8.2.1.2.14 MOSFET Snubber
          15. 8.2.1.2.15 Error Amplifier Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Two-Phase Design Example
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Switching Jitter Root Causes and Solutions
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Error Amplifier Compensation

RCOMP, CCOMP, and CHF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, RCOMP and CCOMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 3.3-V output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain of the LM25119 can be modeled with Equation 40.

Equation 40. LM25119 30126264.gif

where

  • A is the gain of the current sense amplifier which is 10 in the LM25119

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD) and output capacitance (COUT). The corner frequency of this pole calculated with Equation 41.

Equation 41. LM25119 30126265.gif

For RLOAD = 3.3 V / 8 A = 0.413 Ω and COUT = 724 μF (effective) then fP(MOD) = 532 Hz

DC Gain(MOD) = 0.413 Ω / (10 x 8 mΩ) = 5.16 = 14.2 dB

For the 3.3-V design example, the modulator gain versus frequency characteristic is shown in Figure 18.

LM25119 30126216.gifFigure 18. Modulator Gain and Phase

Components RCOMP and CCOMP configure the error amplifier as a Type II configuration. The DC gain of the amplifier is 80 dB with a pole at 0 Hz and a zero at fZEA = 1 / (2 π x RCOMP x CCOMP). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin. For the design example, a conservative target loop bandwidth (crossover frequency) of 11 kHz was selected. The compensation network zero (fZEA) must be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of RCOMP and CCOMP for a desired compensation network zero 1 / (2 π x RCOMP x CCOMP) to be about 1.1 kHz. Increasing RCOMP, while proportionally decreasing CCOMP, increases the error amp gain. Conversely, decreasing RCOMP while proportionally increasing CCOMP, decreases the error amp gain. For the design example, CCOMP was selected as 6800 pF and RCOMP was selected as 36.5 kΩ. These values configure the compensation network zero at 640 Hz. The error amp gain at frequencies greater than fZEA is: RCOMP / RFB2, which is approximately 5.22 (14.3 dB).

The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

LM25119 30126217.pngFigure 19. Error Amplifier Gain and Phase
LM25119 30126218.pngFigure 20. Overall Voltage Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If the K factor is between 2 and 3, the stability must be checked with the network analyzer. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. CHF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of CHF must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency.

Equation 42 offers a good approximation of the location of the pole added by CHF.

Equation 42. fP2 = fZEA × CCOMP / CHF

The value of CHF was selected as 100 pF for the design example.