This design provides 60 dB of gain
with extremely high input impedance at a very low frequency response. The order of
design priorities are as follows:
- The JFE150 bias current is set by
selecting the desired bias current and noise tradeoff (see Figure 6-11). The input-referred noise is dominated by the JFE150 bias current and gain.
To set the bias current point, adjust the source resistance according to Figure 9-3.
- After the bias current is
selected, set the JFET stage gain as high as possible without pushing the device
into the linear region of operation. This is achieved by using the largest drain
resistor (RD) possible while maintaining a minimum of 2 V across the
drain to source nodes. Be aware that the amplifier forces the drain node to
match the noninverting amplifier input in normal closed-loop operation. Both ac
and dc voltages must be considered, but generally, only the dc operating point
on the drain is considered because the ac voltage swing is minimal.
- Set the closed gain according to
RF2 and RS2, as seen in Equation 4. Thermal noise from RS2 directly couples into the circuit;
therefore, small values for this resistor are required.
- CS is required to
block dc voltages from altering the bias point set by source resistor
RS. CS also forms the low-frequency response as
described in Equation 5.