ZHCSE44C august   2015  – may 2023 ISO5852S

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turnoff, Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5852S Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  15. 14Mechanical, Packaging, and Orderable Information

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7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLTAGE SUPPLY
VIT+(UVLO1)Positive-going UVLO1 threshold-voltage input side (VCC1 – GND1)2.25V
VIT-(UVLO1)Negative-going UVLO1 threshold-voltage input side (VCC1 – GND1)1.7V
VHYS(UVLO1)UVLO1 Hysteresis voltage (VIT+ – VIT–) input side0.2V
VIT+(UVLO2)Positive-going UVLO2 threshold-voltage output side (VCC2 – GND2)1213V
VIT–(UVLO2)Negative-going UVLO2 threshold-voltage output side (VCC2 – GND2)9.511V
VHYS(UVLO2)UVLO2 hysteresis voltage (VIT+ – VIT–) output side1V
IQ1Input-supply quiescent current2.84.5mA
IQ2Output-supply quiescent current3.66mA
LOGIC I/O
VIT+(IN, RST)Positive-going input-threshold voltage (IN+, IN–, RST)0.7 × VCC1V
VIT–(IN, RST)Negative-going input-threshold voltage (IN+, IN–, RST)0.3 × VCC1V
VHYS(IN, RST)Input hysteresis voltage (IN+, IN–, RST)0.15 × VCC1V
IIHHigh-level input leakage at (IN+)(1)IN+ = VCC1100µA
IILLow-level input leakage at (IN–, RST)(2)IN– = GND1, RST = GND1-100µA
IPUPullup current of FLT, RDYV(RDY) = GND1, V(FLT) = GND1100µA
V(OL)Low-level output voltage at FLT, RDYI(FLT) = 5 mA0.2V
GATE DRIVER STAGE
V(OUTPD)Active output pulldown voltageI(OUTH/L) = 200 mA, VCC2 = open2V
VOUTHHigh-level output voltageI(OUTH) = –20 mAVCC2 – 0.5VCC2 – 0.24V
VOUTLLow-level output voltageI(OUTL) = 20 mAVEE2 + 13VEE2 + 50mV
I(OUTH)High-level output peak currentIN+ = high, IN– = low,
V(OUTH) = VCC2 - 15 V		1.52.5A
I(OUTL)Low-level output peak currentIN+ = low, IN– = high,
V(OUTL) = VEE2 + 15 V		3.45A
I(OLF)Low-level output current during fault condition130mA
ACTIVE MILLER CLAMP
V(CLP)Low-level clamp voltageI(CLP) = 20 mAVEE2 + 0.015VEE2 + 0.08V
I(CLP)Low-level clamp currentV(CLAMP) = VEE2 + 2.5 V1.62.53.3A
V(CLTH)Clamp threshold voltage1.62.12.5V
SHORT CIRCUIT CLAMPING
V(CLP-OUTH)Clamping voltage
(VOUTH – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA1.11.3V
V(CLP-OUTL)Clamping voltage
(VOUTL – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs, I(OUTL) = 500 mA1.31.5V
V(CLP-CLP)Clamping voltage
(VCLP – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA1.3V
V(CLP-CLAMP)Clamping voltage at CLAMPIN+ = High, IN– = Low,
I(CLP) = 20 mA		0.71.1V
V(CLP-OUTL)Clamping voltage at OUTL
(VCLP – VCC2)		IN+ = High, IN– = Low,
I(OUTL) = 20 mA		0.71.1V
DESAT PROTECTION
I(CHG)Blanking-capacitor charge currentV(DESAT) – GND2 = 2 V0.420.50.58mA
I(DCHG)Blanking-capacitor discharge currentV(DESAT) – GND2 = 6 V914mA
V(DSTH)DESAT threshold voltage with respect to GND28.399.5V
V(DSL)DESAT voltage with respect to GND2, when OUTH or OUTL is driven low0.41V
(1) IIH for IN–, RST pin is zero as they are pulled high internally
(2) IIL for IN+ is zero, as it is pulled low internally