SLLSFC3A March   2020  – December 2021 ISO1640-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6.     Insulation Specifications
    7. 6.6  Safety-Related Certifications
    8. 6.7  Safety Limiting Values
    9. 6.8  Electrical Characteristics
    10. 6.9  Supply Current Characteristics
    11. 6.10 Timing Requirements
    12. 6.11 Switching Characteristics
    13. 6.12 Insulation Characteristics Curves
    14. 6.13 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Isolation Technology Overview
    4. 8.4 Feature Description
      1. 8.4.1 Hot Swap
      2. 8.4.2 Protection Features
    5. 8.5 Isolator Functional Principle
      1. 8.5.1 Receive Direction (Left Diagram of Figure 1-1 )
      2. 8.5.2 Transmit Direction (Right Diagram of Figure 1-1 )
    6. 8.6 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I2C Bus Overview
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Insulation Lifetime
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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Overview

The I2C bus consists of a two-wire communication bus that supports bidirectional data transfer between a master device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL) line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1 Mbps), and high-speed mode (0 to 3.4 Mbps).

The I2C bus operates in bidirectional, half-duplex mode, using open collector outputs to allow for multiple devices to share the bus. When a specific device is ready to communicate on the bus, it can take control pulling the lines low accordingly in order to transmit data. A standard digital isolator or optocoupler is designed to transfer data in a single direction. In order to support an I2C bus, external circuitry is required to separate the bidirectional bus into two unidirectional signal paths. The ISO164x-Q1 devices internally handle the separation and partitioning of the transmit and receive signals, integrating the external circuitry needed and provide the open-collector signals. They provide high electromagnetic immunity and low emissions at low power consumption. Each isolation channel has a logic input and output buffer separated by TI's double capacitive silicon dioxide (SiO2) insulation barrier. When used in conjunction with isolated power supplies, these devices block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry.