ZHCSOW3 September   2020 INA848

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Topology
      2. 8.3.2 Input Common-Mode Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filter Pin
        1. 9.1.1.1 RC Filter Network
        2. 9.1.1.2 RLC Filter Network
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reference Pin
        2. 9.2.2.2 Noise Analysis
          1. 9.2.2.2.1 Reference Voltage Noise Contribution
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 2000 (unless otherwise noted)

N = 3172, mean = –4.678 µV, std dev = 5.715 µV
Figure 7-1 Typical Distribution of Input Offset Voltage
N = 48
Figure 7-3 Input-referred Offset Voltage vs Temperature
N = 527, mean = 17.876 nA, std dev = 2.875 nA
Figure 7-5 Typical Distribution of Input Bias Current
N = 1080, mean = 356.396 ppm, std dev = 186.085 ppm
Figure 7-7 Typical Distribution of Gain Error
VREF = 0 V
Figure 7-9 Input Common-Mode Voltage vs Output Voltage
 
Figure 7-11 Positive Input Bias Current vs Input Common-Mode Voltage
 
Figure 7-13 Input Offset Current vs Temperature
 
Figure 7-15 CMRR vs Frequency (RTI)
GUID-20200826-CA0I-PCGB-GVGV-2KQKGQFDBCD9-low.gif
 
Figure 7-17 Negative PSRR vs Frequency (RTI)
 
Figure 7-19 Current Noise Spectral Density vs Frequency (RTI)
No Load
Figure 7-21 Gain Error vs Temperature
 
Figure 7-23 Large-Signal Step Response
 
Figure 7-25 Small Signal Response
 
Figure 7-27 Supply Current vs Temperature
 
Figure 7-29 Negative Output Voltage Swing vs Output Current
 
Figure 7-31 Short Circuit Current (Source + Sink) vs Temperature
N = 45, mean = 0.116 µV/°C, std dev = 0.102 µV/°C
Figure 7-2 Typical Distribution of Input Offset Voltage Drift
N = 527, mean = 0.1369 nA, std dev = 1.222 nA
Figure 7-4 Typical Distribution of Input Offset Current
N = 527, mean = -0.0840 µV/V, std dev = 0.0420 µV/V
Figure 7-6 Typical CMRR Distribution
N = 7
Figure 7-8 CMRR vs Temperature
 
Figure 7-10 Input Bias Current vs Temperature
 
Figure 7-12 Negative Input Bias Current vs Input Common-Mode Voltage
 
Figure 7-14 Input Offset Current vs Input Common-Mode Voltage
GUID-20200826-CA0I-HWZX-QXVV-XCDZWQP2XGRH-low.gif
 
Figure 7-16 Positive PSRR vs Frequency (RTI)
 
Figure 7-18 Voltage Noise Spectral Density vs Frequency (RTI)
 
Figure 7-20 0.1-Hz to 10-Hz RTI Voltage Noise
 
Figure 7-22 Closed Loop Gain vs Frequency
 
Figure 7-24 Small Signal Response vs Capacitive Loads
 
Figure 7-26 Slew Rate vs Temperature
 
Figure 7-28 Positive Output Voltage Swing vs Output Current
N = 5
Figure 7-30 Input-Referred Offset Voltage vs Settling Time