ZHCSJM1A April   2019  – June 2019 INA818

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      INA818 简化内部原理图
      2.      输入阶段失调电压漂移的典型分布
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics: Table of Graphs
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Setting the Gain
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 EMI Rejection
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Operating Voltage
      6. 8.3.6 Error Sources
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reference Pin
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Resistance Temperature Detector Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.1 Overview

The INA818 is a monolithic, precision instrumentation amplifier incorporating a current-feedback input stage and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how the differential input voltage is buffered by transistors Q1 and Q2 and is forced across resistor RG, which causes a signal current to flow through resistors RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA.