ZHCST11 February   2024 INA185-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 High Bandwidth and Slew Rate
      2. 6.3.2 Bidirectional Current Monitoring
      3. 6.3.3 Wide Input Common-Mode Voltage Range
      4. 6.3.4 Precise Low-Side Current Sensing
      5. 6.3.5 Rail-to-Rail Output Swing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Mode
      2. 6.4.2 Unidirectional Mode
      3. 6.4.3 Bidirectional Mode
      4. 6.4.4 Input Differential Overload
      5. 6.4.5 Shutdown Mode
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Connections
      2. 7.1.2 RSENSE and Device Gain Selection
      3. 7.1.3 Signal Filtering
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Common-Mode Transients Greater Than 26V
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Signal Filtering

Provided that the INA185-Q1 output is connected to a high-impedance input, the best location to filter is at the device output using a simple RC network from OUT to GND. Filtering at the output attenuates high-frequency disturbances in the common-mode voltage, differential input signal, and the INA185-Q1 power-supply voltage. If filtering at the output is not possible, or filtering of only the differential input signal is required, then apply a filter at the input pins of the device. Figure 7-2 provides an example of how a filter can be used on the input pins of the device.

GUID-20240221-SS0I-W0R6-XL9X-KR8023HWHJLZ-low.svg Figure 7-2 Filter at Input Pins

The addition of external series resistance creates an additional error in the measurement, therefore the value of these series resistors must be kept to 10Ω (or less, if possible) to reduce impact to accuracy. The internal bias network (Figure 7-2) present at the input pins creates a mismatch in input bias currents when a differential voltage is applied between the input pins. If additional external series filter resistors are added to the circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch creates a differential error voltage that subtracts from the voltage developed across the shunt resistor. This error results in a voltage at the device input pins that is different than the voltage developed across the shunt resistor. Without the additional series resistance, the mismatch in input bias currents has little effect on device operation. Use Equation 5 to calculate the gain error factor, then use Equation 6 to calculate the amount of error these external filter resistors add to the measurement.

The amount of variance in the differential voltage present at the device input relative to the voltage developed at the shunt resistor is based both on the external series resistance (RF) value as well as the internal input resistor RINT, as shown in Figure 7-2. The reduction of the shunt voltage reaching the device input pins appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A factor can be calculated to determine the amount of gain error that is introduced by the addition of external series resistance. Use Equation 5 to calculate the expected deviation from the shunt voltage to what is measured at the device input pins:

Equation 5. GUID-02EDAFF0-5EBF-42F9-AF53-43F04995DA7F-low.gif

where:

  • RINT is the internal input resistor.
  • RF is the external series resistance.

With the adjustment factor from Equation 5, including the device internal input resistance, this factor varies with each gain version, as shown in Table 7-1. Each individual device gain error factor is shown in Table 7-2.

Table 7-1 Input Resistance
PRODUCTGAINRINT (kΩ)
INA185A12025
INA185A25010
INA185A31005
INA185A42002.5
Table 7-2 Device Gain Error Factor
PRODUCTSIMPLIFIED GAIN ERROR FACTOR
INA185A1GUID-5FB9BEA7-5362-4A1F-9880-B0821968EF3F-low.gif
INA185A2GUID-C26D6702-7976-4CC6-B60C-9D1099C70E3E-low.gif
INA185A3GUID-2C53EE09-39AE-4AFA-AB7B-F0FA850EF2B9-low.gif
INA185A4GUID-221BB02F-1E29-4487-81FF-F2149A9261F6-low.gif

The gain error that can be expected from the addition of the external series resistors can then be calculated based on Equation 6:

Equation 6. GUID-0A092707-4731-4945-B32C-94C91EBFA501-low.gif

For example, using an INA185A2 and the corresponding gain error equation from Table 7-2, a series resistance of 10Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 6, resulting in an additional gain error of approximately 0.89% solely because of the external 10Ω series resistors.