ZHCSE09B June   2015  – March 2024 HD3SS3411-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable and Power Savings
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 AC Coupling Capacitors
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Critical Routes
        2. 7.4.1.2 General Routing/Placement Rules
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 接收文档更新通知
    2. 8.2 支持资源
    3. 8.3 Trademarks
    4. 8.4 静电放电警告
    5. 8.5 术语表
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Critical Routes

  • The high speed differential signals must be routed with great care to minimize signal quality degradation between the connector and the source or sink of the high speed signals by following the guidelines provided in this document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum speed of 10Gbps. These signals are to be routed first before other signals with highest priority.
  • Make sure each differential pair is routed together with controlled differential impedance of 85Ω to 90Ω and 50Ω common-mode impedance. Keep away from other high speed signals. TI recommends to keep the number of vias to a minimum. Separate each pair from adjacent pairs by at least 3 times the signal trace width. Route all differential pairs on the same group of layers (outer layers or inner layers) if not on the same layer. No 90 degree turns on any of the differential pairs. If bends are used on high speed differential pairs, make sure the angle of the bend is greater than 135 degrees.
  • Length matching:
    • Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum. The inter-pair matching of the differential pairs is not as critical as intra-pair matching.
  • Keep high speed differential pair traces adjacent to ground plane.
  • Do not route differential pairs over any plane split.
  • Place the ESD components on the high speed differential lanes as close to the connector as possible in a pass through manner without stubs on the differential path.
  • For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS3411-Q1 pins can be swapped.