ZHCSIK7B July   2018  – October 2023 ESD321

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings – JEDEC Specifications
    3. 6.3 ESD Ratings – IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VRWMReverse stand-off voltageIIO < 50 nA, across operating temperature range3.6V
ILEAKAGELeakage current at 3.6 VVIO = 3.6 V, I/O to GND0.110nA
VBRFBreakdown voltage, I/O to GND (1)IIO = 1 mA4.57.5V
VFWDForward Voltage, GND to I/O (1)IIO = 1 mA0.8V
VHOLDHolding voltage, I/O to GND (2)IIO = 1 mA5.1V
VCLAMPClamping voltageIPP = 6 A (8/20 µs Surge), I/O to GND6.3V
IPP = 16 A (100 ns TLP), I/O to GND6.8V
IPP = 16 A (100 ns TLP), GND to I/O4.7V
RDYNDynamic resistanceI/O to GND, 100 ns TLP, between 10 to 20 A IPP0.13Ω
GND to I/O , 100 ns TLP, between 10 to 20 A IPP0.2
CLINELine capacitance, IO to GNDVIO = 0 V, Vp-p = 30 mV, f = 1 MHz0.91.1pF
VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.