SNLS325D May 2010 – December 2016 DS92LV0421 , DS92LV0422
PRODUCTION DATA.
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage. When the PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a 22-µF cap to Ground to delay the PDB input signal.