ZHCSDB4B MARCH   2013  – January 2015 DS90UH928Q-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 应用图
  5. 修订历史记录
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  DC Electrical Characteristics
    6. 7.6  AC Electrical Characteristics
    7. 7.7  Timing Requirements for the Serial Control Bus
    8. 7.8  Timing Requirements
    9. 7.9  DC and AC Serial Control Bus Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Speed Forward Channel Data Transfer
      2. 8.3.2  Low Speed Back Channel Data Transfer
      3. 8.3.3  Backward Compatible Mode
      4. 8.3.4  Input Equalization
      5. 8.3.5  Common Mode Filter Pin (CMF)
      6. 8.3.6  Power Down (PDB)
      7. 8.3.7  Video Control Signals
      8. 8.3.8  EMI Reduction Features
        1. 8.3.8.1 LVCMOS VDDIO Option
      9. 8.3.9  Built In Self Test (BIST)
        1. 8.3.9.1 BIST Configuration and Status
          1. 8.3.9.1.1 Sample BIST Sequence
        2. 8.3.9.2 Forward Channel and Back Channel Error Checking
      10. 8.3.10 Internal Pattern Generation
        1. 8.3.10.1 Pattern Options
        2. 8.3.10.2 Color Modes
        3. 8.3.10.3 Video Timing Modes
        4. 8.3.10.4 External Timing
        5. 8.3.10.5 Pattern Inversion
        6. 8.3.10.6 Auto Scrolling
        7. 8.3.10.7 Additional Features
      11. 8.3.11 Image Enhancement Features
        1. 8.3.11.1 White Balance
          1. 8.3.11.1.1 LUT Contents
          2. 8.3.11.1.2 Enabling White Balance
        2. 8.3.11.2 Adaptive Hi-FRC Dithering
      12. 8.3.12 Serial Link Fault Detect
      13. 8.3.13 Oscillator Output
      14. 8.3.14 Interrupt Pin (INTB)
      15. 8.3.15 General-Purpose I/O
        1. 8.3.15.1 GPIO[3:0]
        2. 8.3.15.2 GPIO[8:5]
      16. 8.3.16 I2S Audio Interface
        1. 8.3.16.1 I2S Transport Modes
        2. 8.3.16.2 I2S Repeater
        3. 8.3.16.3 I2S Jitter Cleaning
        4. 8.3.16.4 MCLK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clock and Output Status
      2. 8.4.2 FPD-Link Input Frame and Color Bit Mapping Select
      3. 8.4.3 Low Frequency Optimization (LFMODE)
      4. 8.4.4 Mode Select (MODE_SEL)
      5. 8.4.5 Repeater Connections
        1. 8.4.5.1 Repeater Fan-Out Electrical Requirements
      6. 8.4.6 HDCP I2S Audio Encryption
      7. 8.4.7 Repeater Configuration
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Transmission Media
        2. 9.2.2.2 Display Application
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CML Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档 
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings(1)(3)

MIN MAX UNIT
Supply Voltage – VDD33(2) −0.3 4.0 V
Supply Voltage – VDDIO(2) −0.3 4.0 V
LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V
Deserializer Input Voltage −0.3 2.75 V
Junction Temperature 150 °C
48 LLP Package Maximum Power Dissipation Capacity at 25°C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.
(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins(1) ±8000 V
Charged device model (CDM), per AEC Q100-011, all pins ±1250
Machine model (MM) ±250
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000
(ISO10605)
RD = 330 Ω, CS = 150 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000
(ISO10605)
RD = 2 kΩ, CS = 150 pF or 330 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage (VDD33)(1) 3.0 3.3 3.6 V
LVCMOS Supply Voltage (VDDIO)(1)(2) Connect VDDIO to 3.3 V and use 3.3-V IOs 3.0 3.3 3.6 V
Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V
Operating Free Air
 Temperature (TA)
−40 +25 +105 °C
PCLK Frequency (out of TxCLKOUT±) 5 85 MHz
Supply Noise(3) 100 mVP-P
(1) The DS90UH928Q-Q1VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.
(2) VDDIO should not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

7.4 Thermal Information

THERMAL METRIC(1) DS90UH928Q-Q1 UNIT
RHS (WQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 26.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.4
RθJB Junction-to-board thermal resistance 4.3
ψJT Junction-to-top characterization parameter 0.1
ψJB Junction-to-board characterization parameter 4.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
3.3 V LVCMOS I/O
VIH High Level Input Voltage VDDIO = 3.0 V to 3.6 V GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL 2.0 VDDIO V
VIL Low Level Input Voltage GND 0.8 V
IIN Input Current VIN = 0 V or VIN = 3.0 V to 3.6 V −10 ±1 +10 μA
VIH High Level Input Voltage (4) PDB 2.0 VDDIO V
VIL Low Level Input Voltage GND 0.7 V
IIN Input Current VIN = 0 V or VIN = 3.0 V to 3.6 V
(4)
−10 ±1 +10 μA
VOH HIGH Level Output Voltage IOH = -4 mA GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS 2.4 VDDIO V
VOL LOW Level Output Voltage IOL = +4 mA 0 0.4 V
IOS Output Short Circuit Current VOUT = 0 V(5) −55 mA
IOZ Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L −20 +20 μA
1.8 V LVCMOS I/O
VIH High Level Input Voltage VDDIO = 1.71 V to 1.89 V GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL 0.65 * VDDIO VDDIO V
VIL Low Level Input Voltage 0 0.35 * VDDIO V
IIN Input Current VIN = 0 V or VIN = 1.71 V to 1.89 V -10 10 μA
VOH HIGH Level Output Voltage IOH = -4 mA GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS VDDIO - 0.45 VDDIO V
VOL LOW Level Output Voltage IOL = +4 mA 0 0.45 V
IOS Output Short Circuit Current VOUT = 0 V(5) -35 mA
IOZ TRI-STATE® Output Current VOUT = 0 V or VDDIO, PDB = L, -20 20 μA
FPD-LINK LVDS OUTPUT
VOD Output Voltage Swing (single-ended) RL = 100 Ω TxCLK±, TxOUT[3:0]± 350 450 600 mV
VODp-p Differential Output Voltage 900 mV
ΔVOD Output Voltage Unbalance 1 50 mV
VOS Common Mode Voltage 1.0 1.2 1.5 V
ΔVOS Offset Voltage Unbalance 1 50 mV
IOS Output Short Circuit Current VOUT = GND -5 mA
IOZ Output TRI-STATE® Current OEN = GND, VOUT = VDDIO or GND, 0.8 V≤VIN≤1.6 V -500 500 μA
FPD-LINK III RECEIVER
VTH Input Threshold High VCM = 2.1 V (Internal VBIAS) RIN± 50 mV
VTL Input Threshold Low -50 mV
VID Input Differential Threshold 100 mV
VCM Common-mode Voltage 2.1 V
RT Internal Termination Resistance (Differential) 80 100 120 Ω
LOOP-THROUGH MONITOR OUTPUT
VODp-p Differential Output Voltage RL = 100 Ω CMLOUTP, CMLOUTN 360 mV
SUPPLY CURRENT
IDD1 Supply Current
RL = 100Ω,
PCLK = 85MHz
Checkerboard Pattern VDD33= 3.6 V 190 250 mA
IDDIO1 VDDIO = 3.6 V 0.1 1 mA
VDDIO = 1.89 V 0.1 1 mA
IDD2 Random Pattern VDD33= 3.6 V 185 mA
IDDIO2 VDDIO = 3.6 V 0.1 mA
VDDIO = 1.89 V 0.1 mA
IDDZ Supply Current — Power Down PDB = 0 V, All other LVCMOS inputs = 0 V VDD33 = 3.6 V 3 8 mA
IDDIOZ VDDIO = 3.6 V 100 500 μA
VDDIO = 1.89 V 50 250 μA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, Ta = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3.0 V.
(5) IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.

7.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
GPIO
tGPIO,FC GPIO Pulse Width, Forward Channel See (4) GPIO[3:0], PCLK = 5MHz to 85MHz >2/PCLK s
tGPIO,BC GPIO Pulse Width, Back Channel See (4) GPIO[3:0] 20 µs
RESET
tLRST PDB Reset Low Pulse See (4) PDB 2 ms
LOOP-THROUGH MONITOR OUTPUT
EW Differential Output Eye Opening Width RL = 100 Ω, Jitter freq > f/40 RIN± >0.4 UI
EH Differential Output Eye Height >300 mV
FPD-LINK LVDS OUTPUT
tTLHT Low to High Transition Time RL = 100 Ω TxCLK±, TxOUT[3:0]± 0.25 0.5 ns
tTHLT High to Low Transition Time 0.25 0.5 ns
tDCCJ Cycle-to-Cycle Output Jitter PCLK = 5 MHz TxCLK± 170 275 ps
PCLK = 85 MHz 35 55
tTTPn Transmitter Pulse Position 5 MHz≤PCLK≤85 MHz
n=[6:0] for bits [6:0]
See Figure 13
TxOUT[3:0]± 0.5 + n UI
ΔtTTP Offset Transmitter Pulse Position (bit 6 - bit 0) PCLK = 85 MHz <0.1 UI
tDD Delay Latency 147*T T
tTPDD Power Down Delay Active to OFF 900 µs
tTXZR Enable Delay OFF to Active 6 ns
FPD-LINK III INPUT
tDDLT Lock Time(4) 5 MHz≤PCLK≤85 MHz RIN±, LOCK 6 40 ms
LVCMOS OUTPUTS
tCLH Low to High Transition Time CL = 8 pF LOCK, PASS 3 7 ns
tCHL High to Low Transition Time 2 5 ns
BIST MODE
tPASS BIST PASS Valid Time PASS 800 ns
I2S TRANSMITTER
tJ Clock Output Jitter MCLK 2 ns
TI2S I2S Clock Period
Figure 10, (4)(5)
PCLK=5 MHz to 85 MHz I2S_CLK, PCLK = 5MHz to 85MHz >2/PCLK or >77 ns
THC I2S Clock High Time
Figure 10, (5)
I2S_CLK 0.35 TI2S
TLC I2S Clock Low Time
Figure 10, (5)
I2S_CLK 0.35 TI2S
tsr I2S Set-up Time I2S_WC
I2S_D[A:D]
0.2 TI2S
thr I2S Hold Time I2S_WC
I2S_D[A:D]
0.2 TI2S
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, Ta = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by design and is not tested in production.
(5) I2S specifications for tLC and tHC pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.

7.7 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified. (1)(2)
MIN TYP MAX UNIT
fSCL SCL Clock Frequency Standard Mode 0 100 kHz
Fast Mode 0 400 kHz
tLOW SCL Low Period Standard Mode 4.7 µs
Fast Mode 1.3 µs
tHIGH SCL High Period Standard Mode 4.0 µs
Fast Mode 0.6 µs
tHD;STA Hold time for a start or a repeated start condition
(3)
Standard Mode 4.0 µs
Fast Mode 0.6 µs
tSU:STA Set Up time for a start or a repeated start condition
(3)
Standard Mode 4.7 µs
Fast Mode 0.6 µs
tHD;DAT Data Hold Time
(3)
Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
tSU;DAT Data Set Up Time
(3)
Standard Mode 250 ns
Fast Mode 100 ns
tSU;STO Set Up Time for STOP Condition
(3)
Standard Mode 4.0 µs
Fast Mode 0.6 µs
tBUF Bus Free Time
Between STOP and START
(3)
Standard Mode 4.7 µs
Fast Mode 1.3 µs
tr SCL & SDA Rise Time,
(3)
Standard Mode 1000 ns
Fast Mode 300 ns
tf SCL & SDA Fall Time,
(3)
Standard Mode 300 ns
Fast mode 300 ns
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Specification is ensured by design and is not tested in production.

7.8 Timing Requirements

MIN NOM MAX UNIT
tR SDA RiseTime – READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9 430 ns
tF SDA Fall Time – READ 20 ns
tSU;DAT Set Up Time — READ  Figure 9 560 ns
tHD;DAT Hold Up Time — READ  Figure 9 615 ns

7.9 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified. (1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Level SDA and SCL 0.7*
VDDIO
VDD33 V
VIL Input Low Level Voltage SDA and SCL GND 0.3*
VDD33
V
VHY Input Hysteresis >50 mV
VOL SDA or SCL, IOL = 1.25 mA 0 0.36 V
Iin SDA or SCL, Vin = VDDIO or GND -10 +10 µA
tSP Input Filter 50 ns
Cin Input Capacitance SDA or SCL <5 pF
(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
DS90UH928Q-Q1 ECT_CHECKERBOARD.gifFigure 1. Checkerboard Data Pattern
DS90UH928Q-Q1 ECT_CMLOUT.gifFigure 2. CML Output Driver
DS90UH928Q-Q1 ECT_LVCMOS_TRANSITION.gifFigure 3. LVCMOS Transition Times
DS90UH928Q-Q1 ECT_DES_DELAY.gifFigure 4. Latency Delay
DS90UH928Q-Q1 ECT_DES_PDB_DELAY.gifFigure 5. FPD-Link & LVCMOS Power Down Delay
DS90UH928Q-Q1 ECT_OEN_DELAY.gifFigure 6. FPD-Link Outputs Enable Delay
DS90UH928Q-Q1 ECT_PLL_LOCK.gifFigure 7. CML PLL Lock Time
DS90UH928Q-Q1 ECT_FPD_VTH_VTL.gifFigure 8. FPD-Link III Receiver DC VTH/VTL Definition
DS90UH928Q-Q1 ECT_I2S_SH.gifFigure 9. Output Data Valid (Setup and Hold) Times
DS90UH928Q-Q1 ECT_OSS_SH.gifFigure 10. Output State (Setup and Hold) Times
DS90UH928Q-Q1 ECT_RIN_TRANSITION.gifFigure 11. Input Transition Times
DS90UH928Q-Q1 ECT_FPD_VOD.gifFigure 12. FPD-Link Single-Ended and Differential Waveforms
DS90UH928Q-Q1 ECT_FPD_PP.gifFigure 13. FPD-Link Transmitter Pulse Positions
DS90UH928Q-Q1 ECT_DES_IJT.gifFigure 14. Receiver Input Jitter Tolerance
DS90UH928Q-Q1 ECT_BIST_PASS.gifFigure 15. BIST PASS Waveform
DS90UH928Q-Q1 ECT_I2C_TIMING.gifFigure 16. Serial Control Bus Timing Diagram

7.10 Typical Characteristics

DS90UH928Q-Q1 48stream.gifFigure 17. Serializer Output Stream with 48MHz Input Clock
DS90UH928Q-Q1 48delay.gifFigure 18. 48MHz Clock at Serializer and Deserializer