ZHCSEY4 April   2016 DS90UB924-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  DC and AC Serial Control Bus Characteristics
    8. 6.8  Timing Requirements for the Serial Control Bus
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization
      5. 7.3.5  Common Mode Filter Pin (CMF)
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Video Control Signals
      8. 7.3.8  EMI Reduction Features
        1. 7.3.8.1 LVCMOS VDDIO Option
      9. 7.3.9  Built In Self Test (BIST)
        1. 7.3.9.1 BIST Configuration and Status
          1. 7.3.9.1.1 Sample BIST Sequence
        2. 7.3.9.2 Forward Channel and Back Channel Error Checking
      10. 7.3.10 Internal Pattern Generation
        1. 7.3.10.1 Pattern Options
        2. 7.3.10.2 Color Modes
        3. 7.3.10.3 Video Timing Modes
        4. 7.3.10.4 External Timing
        5. 7.3.10.5 Pattern Inversion
        6. 7.3.10.6 Auto Scrolling
        7. 7.3.10.7 Additional Features
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Oscillator Output
      13. 7.3.13 Interrupt Pin (INTB / INTB_IN)
      14. 7.3.14 General-Purpose I/O
        1. 7.3.14.1 GPIO[3:0]
        2. 7.3.14.2 GPIO[8:5]
      15. 7.3.15 I2S Audio Interface
        1. 7.3.15.1 I2S Transport Modes
        2. 7.3.15.2 I2S Repeater
        3. 7.3.15.3 I2S Jitter Cleaning
        4. 7.3.15.4 MCLK
      16. 7.3.16 AV Mute Prevention
      17. 7.3.17 OEN Toggling Limitation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clock and Output Status
      2. 7.4.2 FPD-Link (OpenLDI) Input Frame and Color Bit Mapping Select
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 Mode Select (MODE_SEL)
      5. 7.4.5 Repeater Configuration
        1. 7.4.5.1 Repeater Connections
          1. 7.4.5.1.1 Repeater Fan-Out Electrical Requirements
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transmission Media
        2. 8.2.2.2 Display Application
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 Analog Power Signal Routing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless othewise noted)(1) (3)
MIN MAX UNIT
Supply voltage – VDD33 (2) −0.3 4 V
Supply voltage – VDDIO (2) −0.3 4 V
LVCMOS I/O voltage −0.3 (VDDIO + 0.3) V
Deserializer input voltage −0.3 2.75 V
Junction temperature 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The DS90UB924-Q1 VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.
(3) For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering SNOA549.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins (1) ±8000 V
Charged device model (CDM), per AEC Q100-011, all pins ±1250 V
Machine model (MM) ±250 V
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000 V
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V
(ISO10605)
RD = 330 Ω, CS = 150 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000 V
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V
(ISO10605)
RD = 2 kΩ, CS = 150 pF or 330 pF
 Air Discharge (Pins 40, 41, 44, and 45) ±15000 V
 Contact Discharge (Pins 40, 41, 44, and 45) ±8000 V
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply Voltage (VDD33) (1) 3 3.3 3.6 V
LVCMOS Supply Voltage (VDDIO) (1) (2) Connect VDDIO to 3.3 V and use 3.3-V IOs 3 3.3 3.6 V
Connect VDDIO to 1.8 V and use 1.8-V IOs 1.71 1.8 1.89 V
Operating Free Air
 Temperature (TA)
−40 25 105 °C
PCLK Frequency (out of TxCLKOUT±) 5 96 MHz
Supply Noise (3) 100 mVP-P
(1) The DS90UB924-Q1 VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5 ms with a monotonic rise.
(2) VDDIO must not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the Des shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.

6.4 Thermal Information

THERMAL METRIC (1) DS90UB924-Q1 UNIT
RHS (WQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 26.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.4 °C/W
RθJB Junction-to-board thermal resistance 4.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 4.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
3.3 V LVCMOS I/O
VIH High Level Input Voltage VDDIO = 3.0 V to 3.6 V GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL 2 VDDIO V
VIL Low Level Input Voltage GND 0.8 V
IIN Input Current VIN = 0 V or VIN = 3.0 V to 3.6 V -10 ±1 10 μA
VIH High Level Input Voltage (4) PDB 2 VDDIO V
VIL Low Level Input Voltage GND 0.7 V
IIN Input Current VIN = 0 V or VIN = 3.0 V to 3.6 V
(4)
-10 ±1 10 μA
VOH HIGH Level Output Voltage IOH = -4 mA GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS 2.4 VDDIO V
VOL LOW Level Output Voltage IOL = 4 mA 0 0.4 V
IOS Output Short Circuit Current VOUT = 0 V (5) -55 mA
IOZ Tri-state Output Current VOUT = 0 V or VDDIO, PDB = L -20 20 μA
1.8 V LVCMOS I/O
VIH High Level Input Voltage VDDIO = 1.71 V to 1.89 V GPIO[3:0], REG_GPIO[8:5], LFMODE, MAPSEL, BISTEN, BISTC, INTB_IN, OEN, OSS_SEL 0.65 * VDDIO VDDIO V
VIL Low Level Input Voltage 0 0.35 * VDDIO V
IIN Input Current VIN = 0 V or VIN = 1.71 V to 1.89 V -10 10 μA
VOH HIGH Level Output Voltage IOH = -4 mA GPIO[3:0], REG_GPIO[8:5], MCLK, I2S_WC, I2S_CLK, I2S_D[A:D], LOCK, PASS VDDIO - 0.45 VDDIO V
VOL LOW Level Output Voltage IOL = +4 mA 0 0.45 V
IOS Output Short Circuit Current VOUT = 0 V (5) -35 mA
IOZ TRI-STATE® Output Current VOUT = 0 V or VDDIO, PDB = L, -20 20 μA
FPD-LINK (OpenLDI) LVDS OUTPUT
VOD Output Voltage Swing (single-ended) Register 0x4B[1:0] = b'00
RL = 100 Ω
TxCLK±, TxOUT[3:0]± 140 200 300 mV
Register 0x4B[1:0] = b'01
RL = 100 Ω
220 300 380 mV
VODp-p Differential Output Voltage Register 0x4B[1:0] = b'00
RL = 100 Ω
400 mV
Register 0x4B[1:0] = b'01
RL = 100 Ω
600 mV
ΔVOD Output Voltage Unbalance RL = 100 Ω 1 50 mV
VOS Common Mode Voltage 1 1.2 1.5 V
ΔVOS Offset Voltage Unbalance 1 50 mV
IOS Output Short Circuit Current VOUT = GND -5 mA
IOZ Output TRI-STATE® Current OEN = GND, VOUT = VDDIO or GND, 0.8 V ≤ VIN ≤ 1.6 V -500 500 μA
FPD-LINK III RECEIVER
VTH Input Threshold High VCM = 2.1 V (Internal VBIAS) RIN± 50 mV
VTL Input Threshold Low -50 mV
VID Input Differential Threshold 100 mV
VCM Common-mode Voltage 2.1 V
RT Internal Termination Resistance (Differential) 80 100 120 Ω
SUPPLY CURRENT
IDD33 Supply Current
RL = 100 Ω,
PCLK = 96 MHz
VDD33= 3.6 V 200 260 mA
IDDIO VDDIO = 3.6 V 30 250 μA
VDDIO = 1.89 V 30 250 μA
IDDZ Supply Current — Power Down PDB = 0 V, All other LVCMOS inputs = 0 V VDD33 = 3.6 V 3 8 mA
IDDIOZ VDDIO = 3.6 V 100 500 μA
VDDIO = 1.89 V 50 250 μA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3 V.
(5) IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.

6.6 AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
GPIO
tGPIO,FC GPIO Pulse Width, Forward Channel See (4) GPIO[3:0], PCLK = 5MHz to 96MHz 2/PCLK s
tGPIO,BC GPIO Pulse Width, Back Channel See (4) GPIO[3:0] 20 µs
RESET
tLRST PDB Reset Low Pulse See (4) PDB 2 ms
LOOP-THROUGH MONITOR OUTPUT
EW Differential Output Eye Opening Width(4) RL = 100 Ω, Jitter freq > f/40 CMLOUTP, CMLOUTN 0.4 UI
EH Differential Output Eye Height 300 mV
FPD-LINK (OpenLDI) LVDS OUTPUT
tTLHT Low -to-High Transition Time RL = 100 Ω TxCLK±, TxOUT[3:0]± 0.25 0.5 ns
tTHLT High-to-Low Transition Time 0.25 0.5 ns
tDCCJ Cycle-to-Cycle Output Jitter 5 MHz ≤ PCLK ≤ 96 MHz TxCLK± 40 65 ps
tTTPn Transmitter Pulse Position 5 MHz ≤ PCLK ≤ 96 MHz
n=[6:0] for bits [6:0]
See Figure 13
TxOUT[3:0]± 0.5 + n UI
ΔtTTP Offset Transmitter Pulse Position (bit 6 - bit 0) PCLK = 96 MHz 0.1 UI
tDD Delay Latency 147*T T
tTPDD Power Down Delay Active to OFF 900 µs
tTXZR Enable Delay OFF to Active 6 ns
FPD-LINK III INPUT
tDDLT Lock Time (4) 5 MHz ≤ PCLK ≤ 96 MHz RIN±, LOCK 6 40 ms
LVCMOS OUTPUTS
tCLH Low-to-High Transition Time CL = 8 pF LOCK, PASS 3 7 ns
tCHL High-to-Low Transition Time 2 5 ns
BIST MODE
tPASS BIST PASS Valid Time PASS 800 ns
I2S TRANSMITTER
tJ Clock Output Jitter MCLK 2 ns
TI2S I2S Clock Period
Figure 10, (4) (5)
PCLK=5 MHz to 96 MHz I2S_CLK, PCLK = 5MHz to 96MHz 4/PCLK or 1/12.288MHz ns
THC_I2S I2S Clock High Time Figure 10, (5) I2S_CLK 0.35 TI2S
TLC_I2S I2S Clock Low Time Figure 10, (5) I2S_CLK 0.35 TI2S
tSR_I2S I2S Set-up Time Figure 10, I2S_WC
I2S_D[A:D]
0.2 TI2S
tHR_I2S I2S Hold Time Figure 10 I2S_WC
I2S_D[A:D]
0.2 TI2S
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.
(4) Specification is ensured by design and is not tested in production.
(5) I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.

6.7 DC and AC Serial Control Bus Characteristics

Over 3.3-V supply and temperature ranges unless otherwise specified. (1) (2) (3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Level SDA and SCL 0.7*
VDDIO
VDD33 V
VIL Input Low Level Voltage SDA and SCL GND 0.3*
VDD33
V
VHY Input Hysteresis 50 mV
VOL SDA or SCL, IOL = 1.25 mA 0 0.36 V
Iin SDA or SCL, VIN = VDDIO or GND -10 10 µA
tSP Input Filter 50 ns
Cin Input Capacitance SDA or SCL 5 pF
(1) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD and ΔVOD, which are differential voltages.

6.8 Timing Requirements for the Serial Control Bus

Over 3.3-V supply and temperature ranges unless otherwise specified. (1) (2)
MIN TYP MAX UNIT
fSCL SCL Clock Frequency Standard Mode 0 100 kHz
Fast Mode 0 400 kHz
tLOW SCL Low Period Standard Mode 4.7 µs
Fast Mode 1.3 µs
tHIGH SCL High Period Standard Mode 4.0 µs
Fast Mode 0.6 µs
tHD;STA Hold time for a start or a repeated start condition (3) Standard Mode 4.0 µs
Fast Mode 0.6 µs
tSU:STA Set Up time for a start or a repeated start condition (3) Standard Mode 4.7 µs
Fast Mode 0.6 µs
tHD;DAT Data Hold Time (3) Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
tSU;DAT Data Set Up Time (3) Standard Mode 250 ns
Fast Mode 100 ns
tSU;STO Set Up Time for STOP Condition (3) Standard Mode 4 µs
Fast Mode 0.6 µs
tBUF Bus Free Time
Between STOP and START (3)
Standard Mode 4.7 µs
Fast Mode 1.3 µs
tr SCL & SDA Rise Time, (3) Standard Mode 1000 ns
Fast Mode 300 ns
tf SCL & SDA Fall Time, (3) Standard Mode 300 ns
Fast mode 300 ns
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.
(2) Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended Operating Conditions at the time of product characterization and are not ensured.
(3) Specification is ensured by design and is not tested in production.

6.9 Timing Requirements

MIN NOM MAX UNIT
tR SDA RiseTime – READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9 430 ns
tF SDA Fall Time – READ 20 ns
tSU;DAT Set Up Time – READ   Figure 9 560 ns
tHD;DAT Hold Up Time – READ   Figure 9 615 ns
DS90UB924-Q1 ECT_CHECKERBOARD.gif Figure 1. Checkerboard Data Pattern
DS90UB924-Q1 ECT_CMLOUT.gif Figure 2. CML Output Driver
DS90UB924-Q1 ECT_LVCMOS_TRANSITION.gif Figure 3. LVCMOS Transition Times
DS90UB924-Q1 ECT_DES_DELAY.gif Figure 4. Latency Delay
DS90UB924-Q1 ECT_DES_PDB_DELAY.gif Figure 5. FPD-Link (OpenLDI) and LVCMOS Power Down Delay
DS90UB924-Q1 ECT_OEN_DELAY.gif Figure 6. FPD-Link (OpenLDI) Outputs Enable Delay
DS90UB924-Q1 ECT_PLL_LOCK.gif Figure 7. CML PLL Lock Time
DS90UB924-Q1 ECT_FPD_VTH_VTL.gif Figure 8. FPD-Link III Receiver DC VTH/VTL Definition
DS90UB924-Q1 ECT_I2S_SH.gif Figure 9. Output Data Valid (Setup and Hold) Times
DS90UB924-Q1 i2s_timing_diagram_snls512.gif Figure 10. Output State (Setup and Hold) Times
DS90UB924-Q1 ECT_RIN_TRANSITION.gif Figure 11. Input Transition Times
DS90UB924-Q1 ECT_FPD_VOD.gif Figure 12. FPD-Link (OpenLDI) Single-Ended and Differential Waveforms
DS90UB924-Q1 ECT_FPD_PP.gif Figure 13. FPD-Link (OpenLDI) Transmitter Pulse Positions
DS90UB924-Q1 ECT_DES_IJT.gif Figure 14. Receiver Input Jitter Tolerance
DS90UB924-Q1 ECT_BIST_PASS.gif Figure 15. BIST PASS Waveform
DS90UB924-Q1 ECT_I2C_TIMING.gif Figure 16. Serial Control Bus Timing Diagram

6.10 Typical Characteristics

DS90UB924-Q1 921CMLOUT.gif Figure 17. Serializer Output Stream with 96 MHz Input Clock
DS90UB924-Q1 921-924.gif Figure 18. 96 MHz Clock at Serializer and Deserializer