SNLS344G July   2011  – August 2015 DS80PCI102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Electrical Characteristics — Serial Management Bus Interface
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 7.5.2 Transfer of Data Through the SMBus
      3. 7.5.3 SMBus Transactions
      4. 7.5.4 Writing a Register
      5. 7.5.5 Reading a Register
      6. 7.5.6 EEPROM Programming
        1. 7.5.6.1 Master EEPROM Programming
        2. 7.5.6.2 EEPROM Address Mapping
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 3.3-V or 2.5-V Supply Mode Operation
    2. 9.2 Power Supply Bypass
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

In PCIe Gen-3 applications, the specification requires Rx-Tx link training to establish and optimize signal conditioning settings at 8 Gbps. In link training, the Rx partner requests a series of FIR - preshoot and de-emphasis coefficients (10 Presets) from the Tx partner. The Rx partner includes 7-levels (6 dB to 12 dB) of CTLE followed by a single tap DFE. The link training would pre-condition the signal with an equalized link between the root-complex and endpoint. Note that there is no link training in PCIe Gen-1 (2.5 Gbps) or PCIe Gen-2 (5.0 Gbps) applications. The DS80PCI102 is placed in between the Tx and Rx. It would help extend the PCB trace reach distance by boosting the attenuated signals with it's equalization, so that the signal can be more easily recovered by the downstream Rx. In Gen 3 mode, DS80PCI102 transmit outputs are designed to pass the Tx Preset signaling onto the Rx for the PCIe Gen 3 link to train and optimize the equalization settings. The suggested setting for the DS80PCI102 are EQ = 0x00, VOD = 1.2 Vp-p and DEM = 0 dB. Additional adjustments to increase the EQ or DEM setting should be performed to optimize the eye opening in the Rx partner. See the tables below for Pin Mode and SMBus Mode configurations.

Table 11. Suggested Device Settings in Pin Mode

Channel Pin Mode Settings
EQx[1:0] 0, 0 (Level 1)
DEMx Float, R (Level 10)

Table 12. Suggested Device Settings in SMBus Slave Mode

Register Write Value Comments
0x06 0x18 Enables SMBus Slave Mode Register Control
0x0F 0x00 Set CHA EQ to 0x00.
0x25 0xAD Set CHA VOD to 101'b (1.2 Vp-p).
0x11 0x00 Set CHA DEM to 000'b (0 dB).
0x16 0x00 Set CHB EQ to 0x00.
0x2D 0xAD Set CHB VOD to 101'b (1.2 Vp-p).
0x18 0x00 Set CHB DEM to 000'b (0 dB).

8.2 Typical Application

The DS80PCI102 extends PCB trace and cable reach in PCIe Gen1, 2 and 3 applications by applying equalization to compensate for the insertion loss of the trace or cable. In Gen 3 mode, the device aids specifically in the equalization link training to improve the margin and overall eye inside the Rx. The DS80PCI102 can be used on the motherboard, mid plane (riser card), end-point target cards, and active cable assemblies. The capability of the DS80PCI102 performance is shown in the following two test setup connections.

DS80PCI102 ds80pci102_test_setup_1.gifFigure 10. Test Setup Connections Diagram
DS80PCI102 ds80pci102_test_setup_2.gifFigure 11. Test Setup Connections Diagram

8.2.1 Design Requirements

As with any high speed design, there are many factors which influence the overall performance. The following list indicates critical areas for consideration during design.

  • Use 100-Ω impedance traces. Length matching on the P and N traces should be done on the single-end segments of the differential pair.
  • Use uniform trace width and trace spacing for differential pairs.
  • Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
  • For Gen3, AC-coupling capacitors of 220 nF are recommended, maximum body size is 0402, and add cutout void on GND plane below the landing pad of the capacitor in order to reduce parasitic capacitance to GND.
  • Back-drill connector vias and signal vias to minimize stub length.
  • Use Reference plane vias to ensure a low inductance path for the return current.

8.2.2 Detailed Design Procedure

The DS80PCI102 should be placed at an offset location and close to the Rx with respect to the overall channel attenuation. The suggested settings are recommended as a starting point for most applications. Once these settings are configured, additional adjustments of the DS80PCI102 EQ or DE may be required to optimize the repeater performance. The CTLE and DFE coefficient in the Rx can also be adjusted to further improve the eye opening.

8.2.3 Application Curves

DS80PCI102 30119831.png
A. DS80PCI102 Settings:
EQ[1:0] = [R, R] or 0x15, Dem[1:0] = [Float, Float]
Figure 12. TL = 20-Inch 4–Mil FR4 Trace
DS80PCI102 30119834.png
A. DS80PCI102 Settings:
EQ[1:0] = [R, R] or 0x15, DEM[1:0] = [Float, Float]
Figure 14. TL1 = 20-Inch 4–Mil FR4 Trace, TL2 = 15-Inch 4–Mil FR4 Trace
DS80PCI102 30119832.png
A. DS80PCI102 Settings:
EQ[1:0] = [Float, R] or 0x1F, DEM[1:0] = [Float, Float]
Figure 13. TL = 35-Inch 4–Mil FR4 Trace
DS80PCI102 30119835.png
A. DS80PCI102 Settings:
EQ[1:0] = [R, 1] or 0x0F, DEM[1:0] = [Float, Float]
Figure 15. TL1 = 30-Inch 4–Mil FR4 Trace, TL2 = 15-Inch 4–Mil FR4 Trace