ZHCSM45 june   2023 DS320PR1601

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD and Latchup Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
      4. 7.3.4 Five-Level Control Inputs
      5. 7.3.5 Integrated Capacitors
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
  9. 8 Programming
    1. 8.1 Pin Configurations for Lanes
    2. 8.2 SMBUS/I2C Register Control Interface
      1. 8.2.1 Shared Registers
      2. 8.2.2 Channel Registers
    3. 8.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 PCIe x16 Lane Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.2 Channel Registers

Table 8-6 RX Detect Status Register (Channel Register Base + Offset = 0x00)
Bit Field Type Reset Description
7 rx_det_comp_p R 0x0 Rx detect positive data pin status:

0: not detected

1: detected – the value is latched
6 rx_det_comp_n R 0x0 Rx detect negative data pin status:

0: not detected

1: detected – the value is latched
5-0 RESERVED R 0x0 Reserved
Table 8-7 EQ Gain Control Register (Channel Register Base + Offset = 0x01)
Bit Field Type Reset Description
7 eq_stage1_bypass R/W 0x0

Enable EQ stage 1 bypass:

0: bypass disabled

1: bypass enabled
6 eq_stage1_3 R/W 0x0

EQ boost stage 1 control

See Table 7-1 for details
5 eq_stage1_2 R/W 0x0
4 eq_stage1_1 R/W 0x0
3 eq_stage1_0 R/W 0x0
2 eq_stage2_2 R/W 0x0

EQ boost stage 2 control

See Table 7-1 for details
1 eq_stage2_1 R/W 0x0
0 eq_stage2_0 R/W 0x0
Table 8-8 Mute EQ Control Register (Channel register base + Offset = 0x02)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6-4 RESERVED R/W 0x0 Reserved
3 mute_eq R/W 0x0 Mute EQ output
2-0 RESERVED R 0x0 Reserved
Table 8-9 EQ Gain / Flat Gain Control Register (Channel Register Base + Offset = 0x03)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 eq_profile_3 R/W 0x0

EQ mid-frequency boost profile

See Section 7.3.1 for details

5 eq_profile_2 R/W 0x0
4 eq_profile_1 R/W 0x0
3 eq_profile_0 R/W 0x0
2 flat_gain_2 R/W 0x1

Flat gain select:

See Table 7-3 for details

1 flat_gain_1 R/W 0x0
0 flat_gain_0 R/W 0x1
Table 8-10 Rx Detect Control Register (Channel Register Base + Offset = 0x04)
Bit Field Type Reset Description
7-3 RESERVED R 0x0 Reserved
2 mr_rx_det_man R/W 0x0

Manual override of rx_detect_p/n decision:

0: Rx detect state machine is enabled

1: Rx detect state machine is overridden – always valid RX termination detected
1 en_rx_det_count R/W 0x0 Enable additional Rx detect polling

0: additional Rx detect polling disabled

1: additional Rx detect polling enabled
0 sel_rx_det_count R/W 0x0

Select number of valid Rx detect polls – gated by en_rx_det_count = 1

0: device transmitters poll until 2 consecutive valid detections

1: device transmitters poll until 3 consecutive valid detections
Table 8-11 PD Override Register (Channel Register Base + Offset = 0x05)
Bit Field Type Reset Description
7 device_en_override R/W 0x0 Enable power down overrides through SMBus/I2C

0: manual override disabled

1: manual override enabled
6-0 device_en R/W 0b111111 Manual power down of redriver various blocks – gated by device_en_override = 1

111111: all blocks are enabled

000000: all blocks are disabled
Table 8-12 Bias Register (Channel Register Base + Offset = 0x06)
Bit Field Type Reset Description
5-3 Bias current R/W 0b100 Control bias current
7,6,2-0 Reserved R/W 0b00000 Reserved