ZHCSKE4C october   2016  – december 2020 DS280MB810

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements – Serial Management Bus Interface
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Data Path Operation
      2. 8.3.2 AC-coupled Receiver Inputs
      3. 8.3.3 Signal Detect
      4. 8.3.4 2-Stage CTLE
      5. 8.3.5 Driver DC Gain Control
      6. 8.3.6 2x2 Cross-point Switch
      7. 8.3.7 Configurable SMBus Address
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Slave Mode Configuration
      2. 8.4.2 SMBus Master Mode Configuration (EEPROM Self Load)
    5. 8.5 Programming
      1. 8.5.1 Transfer of Data with the SMBus Interface
    6. 8.6 Register Maps
      1. 8.6.1 Register Types: Global, Shared, and Channel
      2. 8.6.2 Global Registers: Channel Selection and ID Information
      3. 8.6.3 Shared Registers
      4. 8.6.4 Channel Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Backplane and Mid-Plane Reach Extension
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Front-Port Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Pattern Generator Characteristics
        2. 9.2.3.2 Equalizing Moderate Pre-Channel Loss
        3. 9.2.3.3 Equalizing High Pre-Channel Loss
        4. 9.2.3.4 Equalizing High Pre-Channel Loss and Moderate Post-Channel Loss
    3. 9.3 Initialization Set Up
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 Stripline Example
      2. 11.2.2 Microstrip Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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8.6.4 Channel Registers

Table 8-4 Channel Register Map
Addr [HEX]BitDefault [HEX]ModeEEPROMFieldDescription
0x000x00General
70RWNCLK_CORE_DISAB1: Disables 10 M core clock. This is the main clock domain for all the state machines.
0: Normal operation
60RWNCLK_REGS_EN1: Force enable the clock to the registers. Normally, the register clock is enabled automatically on a needed basis.
0: Normal operation
50RWNRESERVEDRESERVED
40RWNCLK_REF_DISAB1: Disables the 25 MHz CAL_CLK domain.
0: Normal operation
30RWNRST_CORE1: Reset the 10 M core clock domain. This is the main clock domain for all the state machines.
0: Normal operation
20RWSCNRST_REGS1: Reset channel registers to power-up defaults.
0: Normal operation
10RWNRESERVEDRESERVED
00RWNRST_CAL_CLK1: Resets the 25 MHz reference clock domain.
0: Normal operation
0x010x01SIG_DET
70RNSIGDETSignal detect status.
1: Signal detected at RX inputs.
0: No signal detected at RX inputs.
60RNSIGDET_ADJACENTSignal detect status of adjacent channel. "Adjacent," referring to channel N+1 if N is even, or channel N-1 if N is odd.
1: Signal detected at RX inputs of adjacent channel.
0: No signal detected at RX inputs.
50RNRESERVEDRESERVED
40RNRESERVEDRESERVED
30RNRESERVEDRESERVED
20RNRESERVEDRESERVED
10RNRESERVEDRESERVED
01RNRESERVEDRESERVED
0x020x00
70RNRESERVEDRESERVED
60RNRESERVEDRESERVED
50RNRESERVEDRESERVED
40RNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x030x80CTLE_BOOST
71RWYEQ_BW[1]EQ stage one buffer current (strength) control. Impacts EQ bandwidth. 2'b11 yields highest bandwidth, 2'b00 yields lowest bandwidth. Refer to the Programming Guide for more information.
60RWYEQ_BW[0]
50RWYEQ_BST2[2]EQ boost stage 2 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information.
40RWYEQ_BST2[1]
30RWYEQ_BST2[0]
20RWYEQ_BST1[2]EQ boost stage 1 controls. Directly goes to analog. No override bit is needed. Refer to the Programming Guide for more information.
10RWYEQ_BST1[1]
00RWYEQ_BST1[0]
0x040x90
71RWNRESERVEDRESERVED
60RWNEQ_PD_SD1: Power down signal detect
0: Normal operation
50RWYEQ_HIGH_GAIN1: Enable EQ high gain
0: Enable EQ low gain
41RWYEQ_EN_DC_OFFRESERVED
30RWYEQ_PD_EQ1: Power down EQ
0: Enable EQ
20RWNRESERVEDRESERVED
10RWYBG_SEL_IPP100[2]CTLE bias programming. BG_SEL_IPP100[1:0] is in Reg_0x0F[5:4].
00RWYEQ_EN_BYPASS1: Enable EQ boost stage 1 (BST1) bypass.
0: Normal operation, signal travels through boost stage 1 (BST1).
0x050x04SIG_DET_CONFIG
70RWYEQ_SD_PRESET1: Force signal detect result to 1.
0: Normal operation
This bit should not be set if 0x05[6] is also set.
60RWYEQ_SD_RESET1: Force signal detect result to 0.
0: Normal operation
This bit should not be set if 0x05[7] is also set.
50RWYEQ_REFA_SEL[1]Signal detect assert thresholds. Refer to the Programming Guide for more information.
40RWYEQ_REFA_SEL[0]
30RWYEQ_REFD_SEL[1]Signal detect de-assert thresholds. Refer to the Programming Guide for more information.
21RWYEQ_REFD_SEL[0]
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x060xC0GPIO2 Config
71RWYDRV_SEL_VOD[1]Driver VOD adjust (DC gain). Refer to the Programming Guide for more information.
61RWYDRV_SEL_VOD[0]
50RWYDRV_EQ_PD_OV1: Driver and equalizer power down manually with Reg_0x06[3] and Reg_0x04[3], respectively.
0: Driver and equalizer are powered down or up by default when LOS=1/0.
40RWYDRV_SEL_MUTE
_OV		Driver mute override:
1: Use register 0x06[1] for mute control.
0: Normal operation. Mute is automatically controlled by signal detect.
30RWYDRV_PD1: Power down the driver.
0: Normal operation, driver power on or off is controlled by signal detect.
20RWYDRV_PD_CM_LOOP1: Disable the driver’s common mode loop control circuit.
0: Normal operation, common mode loop enabled.
10RWYDRV_SEL_MUTE1: Mute driver if override bit is enabled.
0: Normal operation
00RWYDRV_SEL_SOURCESelect the signal source for the current channel's driver using the cross-point.
1: Transmit the signal from the adjacent channel.
0: Transmit the signal from the local channel.
0x070x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWYMUX_INV_PIN_CTRLInvert the mux pin control. Only applicable if Shared Reg_0x05[1]=1.
For channels 0, 1, 4, and 5 (controlled by MUXSEL0):
0: If MUXSEL0=0, channel is in straight-thru mode. If MUXSEL0=1, channel output is from adjacent channel's EQ.
1: If MUXSEL0=1, channel is in straight-thru mode. If MUXSEL0=0, channel output is from adjacent channel's EQ.

For channels 2, 3, 6, and 7 (controlled by MUXSEL1):
0: If MUXSEL1=0, channel is in straight-thru mode. If MUXSEL1=1, channel output is from adjacent channel's EQ.
1: If MUXSEL1=1, channel is in straight-thru mode. If MUXSEL1=0, channel output is from adjacent channel's EQ.
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x080x50
70RWYRESERVEDRESERVED
61RWYRESERVEDRESERVED
50RWYRESERVEDRESERVED
41RWYRESERVEDRESERVED
30RWYBG_SEL_IPTAT251: Increases the current to the CTLE by 5%.
0: Default
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x090x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x0A0x30
70RWNRESERVEDRESERVED
60RWYSD_EN_FAST1: Fast signal detect enabled.
0: Fast signal detect disabled.
51RWYSD_REF_HIGHSignal detect threshold controls:
11: Normal operation
10: Signal detect assert or de-assert thresholds reduced.
01: Signal detect assert or de-assert thresholds reduced.
00: Signal detect assert or de-assert thresholds reduced.
41RWYSD_GAIN
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x0B0x1A
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
41RWYRESERVEDRESERVED
31RWYRESERVEDRESERVED
20RWYRESERVEDRESERVED
11RWYRESERVEDRESERVED
00RWYRESERVEDRESERVED
0x0C0x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWYRESERVEDRESERVED
20RWYRESERVEDRESERVED
10RWYRESERVEDRESERVED
00RWYRESERVEDRESERVED
0x0D0x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWYRESERVEDRESERVED
20RWYRESERVEDRESERVED
10RWYRESERVEDRESERVED
00RWYRESERVEDRESERVED
0x0E0x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED
0x0F0x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWYBG_SEL_IPP100[1]CTLE bias programming. BG_SEL_IPP100[2] is in Reg_0x04[1].
000: 0% additional current (Default)
001: 5% additional current
010: 10% additional current
011: 15% additional current
100: 20% additional current
101: 25% additional current
110: 30% additional current
111: 35% additional current
40RWYBG_SEL_IPP100[0]
30RWYBG_SEL_IPH200
_v1[1]		Program pre-driver bias current:
00: 0% additional current (Default)
01: 12.5% additional current
10: 25% additional current
11: 37.5% additional current
20RWYBG_SEL_IPH200
_v1[0]
10RWYBG_SEL_IPH200
_v0[1]		Program driver bias current:
00: 0% additional current (Default)
01: 12.5% additional current
10: 25% additional current
11: 37.5% additional current
00RWYBG_SEL_IPH200
_v0[0]
0x100x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWYRESERVEDRESERVED
40RWYRESERVEDRESERVED
30RWYRESERVEDRESERVED
20RWYRESERVEDRESERVED
10RWYRESERVEDRESERVED
00RWYRESERVEDRESERVED
0x11-0x190x00
70RWNRESERVEDRESERVED
60RWNRESERVEDRESERVED
50RWNRESERVEDRESERVED
40RWNRESERVEDRESERVED
30RWNRESERVEDRESERVED
20RWNRESERVEDRESERVED
10RWNRESERVEDRESERVED
00RWNRESERVEDRESERVED