ZHCSME1C August   2018  – June 2021 DS250DF230

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Data Path Operation
      2. 8.3.2  Signal Detect
      3. 8.3.3  Continuous Time Linear Equalizer (CTLE)
      4. 8.3.4  Variable Gain Amplifier (VGA)
      5. 8.3.5  Cross-Point Switch
      6. 8.3.6  Decision Feedback Equalizer (DFE)
      7. 8.3.7  Clock and Data Recovery (CDR)
        1. 8.3.7.1 CDR Bypass (Raw) Mode
        2. 8.3.7.2 CDR Fast Lock Mode
      8. 8.3.8  Calibration Clock
      9. 8.3.9  Differential Driver With FIR Filter
        1. 8.3.9.1 Setting the Output VOD, Pre-Cursor, and Post-Cursor Equalization
        2. 8.3.9.2 Output Driver Polarity Inversion
        3. 8.3.9.3 Slow Slew Rate
      10. 8.3.10 Debug Features
        1. 8.3.10.1 Pattern Generator
        2. 8.3.10.2 Pattern Checker
        3. 8.3.10.3 Eye-Opening Monitor
      11. 8.3.11 Interrupt Signals
    4. 8.4 Device Functional Modes
      1. 8.4.1 Supported Data Rates
      2. 8.4.2 SMBus Master Mode
      3. 8.4.3 Device SMBus Address
    5. 8.5 Programming
      1. 8.5.1 Bit Fields in the Register Set
      2. 8.5.2 Writing to and Reading from the Global/Shared/Channel Registers
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Front-Port Jitter Cleaning Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Cable Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Backplane and Mid-Plane Applications
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
  13. 13Electrostatic Discharge Caution
  14. 14术语表
  15. 15Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER CONSUMPTION
WChannel Power Consumption Per Active Channel Active mode with CTLE, Tx FIR, full DFE and Crosspoint enabled. Idle power consumption not included. 256 347 mW
Active mode with CTLE, Tx FIR, and full DFE enabled. Crosspoint disabled. Idle power consumption not included. 248 mW
Active mode with CTLE, Tx FIR, and partial DFE enabled(taps 1-2 only). Crosspoint and DFE taps 3-5 disabled. Idle power consumption not included. 235 mW
Active mode with CTLE, and Tx FIR enabled. DFE and crosspoint disabled. Idle power consumption not included. 226 mW
Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Crosspoint enabled. Idle power consumption not included. 380 445 mW
Assuming CDR acquiring lock with CTLE, full DFE, Tx FIR, Driver, and Crosspoint disabled. Idle power consumption not included. 333 mW
WPRBS PRBS Checker Power Consumption only Per Channel 200 mW
PRBS Generator Power Consumption only Per Channel 190 mW
WStatic_Total Total Idle Power Consumption Idle/Static mode. Power supplied, no high-speed data present at inputs, channel automatically powered down. 165 mW
IStatic_Total Idle mode total device supply current consumption Idle/Static mode. Power supplied, no high-speed data present at inputs, channel automatically powered down. 66 100 mA
ITotal Active Mode Total Device Supply Current Consumption Active mode with CTLE, Tx FIR, full DFE and Crosspoint enabled. 271 361 mA
Active mode with CTLE, Tx FIR, and full DFE enabled. Crosspoint disabled. 265 mA
Active mode with CTLE, Tx FIR, and partial DFE enabled(taps 1-2 only). Crosspoint and DFE taps 3-5 disabled. 255 mA
Active mode with CTLE, and Tx FIR enabled. DFE and crosspoint disabled. 247 mA
GENERAL DEVICE-LEVEL SPECIFICATIONS
Rbaud Supported input data rate Full-rate (divide-by-1) mode of operation. 19.6 25.8 Gbps
Half-rate (divide-by-2) mode of operation. 9.8 12.9 Gbps
Quarter-rate (divide-by-4) mode of operation. 4.9 6.45 Gbps
tEEPROM EEPROM configuration load time Single device reading its configuration from an EEPROM. Common channel configuration. This time scales with the number of devices reading from the same EEPROM. 15(1) ms
EEPROM configuration load time Single device reading its configuration from an EEPROM. Unique-channel configuration. This time scales with the number of devices reading from the same EEPROM. 40(1) ms
tPOR Power-on reset assertion-time Internal power-on reset (PoR) stretch between stable power supply and de-assertion of internal PoR. The SMBus address is latched on the completion of the PoR stretch, and SMBus accesses are permitted. 50 ms
HIGH-SPEED DIFFERENTIAL OUTPUTS (TXnP, TXnN)
VOD Output differential voltage amplitude Measured with c(0)=4 setting (REG_0x3D[6:0]=0x04, REG_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. 392 mVppd
Output differential voltage amplitude Measured with c(0)=31 setting (REG_0x3D[6:0]=0x1F, REG_0x3E[6:0]=0x40, REG_0x3F[6:0]=0x40). Differential measurement using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. 1195 mVppd
VOD_Raw_L Output differential voltage amplitude under Raw Mode,  low swing setting Raw Mode(CDR Bypassed), low swing setting(REG_0xD[0]=0), differential measurement using 8T pattern(eight 1s followed by eight 0s) at 25.78125Gbps and 9.8304Gbps with TXPn and TXNn terminated by 50 Ohms to GND.
RPH=REG_0x1A[7:6]=0		 602 mVppd
VOD_Raw_H Output differential voltage amplitude under Raw Mode,  high swing setting Raw Mode(CDR Bypassed), high swing setting(REG_0xD[0]=1),,differential measurement using 8T pattern(eight 1s followed by eight 0s) at 25.78125Gbps and 9.8304Gbps with TXPn and TXNn terminated by 50 Ohms to GND.
RPH=REG_0x1A[7:6]=0x3		 919 mVppd
VOD_Idle Differential output amplitude with TX disabled 6.1 mVppd
Vcm_TX DC common-mode output voltage With respect to signal ground. Measured using an 8T pattern (eight 1s followed by eight 0s) at 25.78125 Gbps with TXPn and TXNn terminated by 50 Ohms to GND. Measured for c(-1)=c(1)=0 and VOD settings in the range of 600 mVppd to 1200 mVppd. 1.01 V
Vcm_TX_AC Common-mode AC output noise With respect to signal ground. Measured with PRBS9 data pattern. Measured with a 33GHz (-3dB) low-pass filter.  7.4 mV, RMS
tr, tf Output transition-time 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 25.78125 Gbps. Measured for ~750 mVppd output amplitude and no equalization: REG_0x3D=+13, REG_0x3E=0, REG_0x3F=0 17.5 ps
Output transition-time, Low slew rate setting Slow slew rate setting(REG_0x3D[5]=1), 20%-to-80% rise time and 80%-to-20% fall time on a clock-like {11111 00000} data pattern at 9.8304 Gbps. Measured for ~750 mVppd output amplitude and no equalization: REG_0x3D=+13, REG_0x3E=0, REG_0x3F=0 24 ps
RLSDD22 Differential output return loss, SDD22(2) Between 50 MHz and 5 GHz -15.9 dB
Differential output return loss, SDD22(2) Between 5 GHz and 12.9 GHz -13 dB
RLSCD22 Differential to common-mode output return loss, SCD22(2) Between 50 MHz and 12.9 GHz -24 dB
RLSDC22 Common-mode to differential output return loss, SDC22(2) Between 50 MHz and 12.9 GHz -24 dB
RLSCC22 Common-mode output return loss, SCC22(2) Between 50 MHz and 10 GHz -8 dB
Common-mode output return loss, SCC22(2) Between 10 GHz and 12.9 GHz -8.5 dB
RETIMER TIMING SPECIFICATIONS
tD Input-to-output latency (propagation delay) through a channel No Crosspoint; CDR enabled and locked. 4.5 UI + 175 ps ps
Crosspoint enabled; CDR enabled and locked. 4.5 UI + 220 ps ps
No crosspoint; CDR in raw mode. 140 ps
tD_V Variation of Input-to-output latency Crosspoint enabled; CDR enabled and locked. ± 50 ps
tSK Channel-to-channel interpair skew Latency difference between channels at full-rate. 30 ps
tLock CDR lock acquisition-time, Normal Lock Mode Measured at 25.78125 Gbps, Adapt mode 2(REG_0x31[6:5]=0x2) <100 ms
CDR lock acquisition-time, Fast Lock Mode Measured at 25.78125 Gbps, Adapt mode 2 (REG_0x31[6:5]=0x2). Fast Lock Mode Enabled (REG_0xAC[7] = 1). Adaptation process still runs to find the best CTLE/DFE values after CDR lock is declared. <10 ms
CDR lock acquisition-time, Fast Lock Mode Measured at 25.78125 Gbps, Adapt mode 0 (Reg_0x31[6:5]=0x0), Fast Lock Mode Enabled (REG_0xAC[7] = 1). Adaptation process still runs to find the best CTLE/DFE values after CDR lock is declared. <2 ms
tEQ_Adapt Total EQ Adaptation Completion Time (includes tLOCK) Measured at 25.78125 Gbps, Adapt mode 2 (REG_0x31[6:5]=0x2)  (3) (4) <3 s
RETIMER JITTER SPECIFICATIONS
JTJ Output Total jitter (TJ) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded 0.16 UIpp @ 1E-12
JRJ Output Random Jitter (RJ) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded 6.8 mUI RMS
JDCD Output Duty Cycle Distortion (DCD) Measured at 25.78125 Gbps to a probability level of 1E-12 with PRBS11 data pattern an evaluation board traces de-embedded 3.7 mUIpp
HIGH-SPEED DIFFERENTIAL INPUTS (RXnP, RXnN)
VIDMax Maximum tolerable input differential voltage For normal operation 1200 mVppd
Vcm-Self Self-generated input common mode 1.79 V
RLSDD11 Differential input return loss, SDD11(5) Between 50 MHz and 3.69 GHz -20 dB
Differential input return loss, SDD11(5) Between 3.69 GHz and 12.9 GHz -13 dB
RLSDC11 Common-mode to differential input return loss, SDC11(5) Between 50 MHz and 12.9 GHz -23 dB
RLSCD11 Differential to common-mode input return loss, SCD11(5) Between 50 MHz and 12.9 GHz -23 dB
RLSCC11 Common-mode input return loss, SCC11(5) Between 150 MHz and 10 GHz -11 dB
Common-mode input return loss, SCC11(5) Between 10 GHz and 12.9 GHz -8 dB
VSDAT AC signal detect assert (ON) threshold level Minimum input peak-to-peak amplitude level at device pins required to assert signal detect. Assumes default assert threshold setting. Measured at 25.78125 Gbps with PRBS7.  145 mVppd
VSDDT AC signal detect de-assert (OFF) threshold level Maximum input peak-to-peak amplitude level at device pins which causes signal detect to de-assert. Assumes default de-assert threshold setting . Measured at 25.78125 Gbps with PRBS7.  84 mVppd
RETIMER CLOCK AND DATA RECOVERY SPECIFICATIONS
BWPLL PLL bandwidth Measured at 9.8304 Gbps with PRBS7 data pattern 4 MHz
PLL bandwidth Measured at 25.78125 Gbps with PRBS7 data pattern 4.7 MHz
JPEAK Jitter peaking Measured at 9.8304 Gbps with PRBS7 data pattern. 0.5 dB
Jitter peaking Measured at 25.78125 Gbps with PRBS7 data pattern.  0.5 dB
JTOL Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency = 190 KHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 9 UIpp
Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency = 940 KHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 1 UIpp
Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency > 15MHz, 30dB input channel loss, PRBS31 data pattern, ~800 mVppd launch amplitude, and 0.18 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 0.33 UIpp
TEMPLOCK- CDR stay-in-lock junction temperature range, negative ramp. Maximum junction temperature change below initial CDR lock acquisition temperature 110 °C junction temperature starting, ramp rate -3°C/minute, 12 layer PCB 150 °C
TEMPLOCK+ CDR stay-in-lock junction temperature range, positive ramp. Maximum junction temperature change above initial CDR lock acquisition temperature -40 °C junction temperature starting, ramp rate +3°C/minute, 12 layer PCB 150 °C
RECOVERED CLOCK SPECIFICATIONS
RCKf Recovered Clock frequency on RCK0 pin Measured with input data rate as 24.33024 Gbps or 12.16512 Gbps or 10.1376 Gbps 9.8304 Gbps or 6.144 Gbps or 4.9152 Gbps 30.72 MHz
Recovered Clock frequency on RCK0 pin Measured with input data rate as 25.78125Gbps or 10.3125Gbps 32.2265625 MHz
RCKPhase
RCKf Phase Noise Performance(6) 

 		 <=100 Hz < -59 dBc/Hz
Between 100 Hz and 1 kHz < -84 dBc/Hz
Between 1 kHz and 10 kHz < -103 dBc/Hz
>10 kHz < -122 dBc/Hz
CALIBRATION CLOCK SPECIFICATIONS
CLKf Calibration clock frequency Option 1: 30.72 MHz 30.72 MHz
Calibration clock frequency Option 2: 25 MHz 25 MHz
CLKppm Calibration clock PPM tolerance -100 100 PPM
CLKIDC Calibration clock input duty cycle 40 50 60 Percent
CLKODC Intrinsic calibration clock duty cycle distortion Intrinsic duty cycle distortion of chip calibration clock output at the CAL_CLK_OUT pin, assuming 50% duty cycle on CAL_CLK_IN pin. 45 50 55 Percent
CLKnum Number of devices which can be cascaded from CAL_CLK_OUT to CAL_CLK_IN Assumes worst-case 60%/40% input duty cycle on the first device. CAL_CLK_OUT from first device connects to CAL_CLK_IN of second device, and so on until the last device. 20 N/A
LVCMOS DC SPECIFICATIONS
VIH Input high-level voltage 2.5 V LVCMOS pins 1.75 VDD V
3.3 V LVCMOS pin (READ_EN_N) 1.75 3.6 V
VIL Input low-level voltage 2.5 V LVCMOS pins GND 0.7 V
3.3 V LVCMOS pin (READ_EN_N) GND 0.8 V
Vth High-level(1) input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.98 x VDD V
Float level input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.69 x VDD V
10K to GND input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.25 x VDD V
Low-level (0) input voltage 4-level pins ADDR0, ADDR1, EN_SMB and THR 0.1 V
VOH High-level output voltage IOH = 4mA 2 V
VOL Low-level output voltage IOL = -4mA 0.4 V
IIH Input high leakage current Vinput = VDD, Open drain pins 70 uA
Input high leakage current Vinput = VDD and CAL_CLK_IN pins 65 uA
Input high leakage current Vinput = VDD, ADDR[1:0] and EN_SMB pins 65 uA
Input high leakage current Vinput = VDD, READ_EN_N 15 uA
IIL Input low leakage current Vinput = 0V, Open drain pins –15 uA
Input low leakage current Vinput = 0V, CAL_CLK_IN pins –15 uA
Input low leakage current Vinput = 0V, ADDR[1:0], READ_EN_N, and EN_SMB pins –115 uA
(1) From low assertion of READ_EN_N to low_assertion of ALL_DONE_N. Does not include Power-On Reset time
(2) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9 GHz between DS250DF230 and the measurement instrument.
(3) Prior to EQ adaptation completion, retimer output may not be error-free.
(4) There may be an observed increase from the typical tEQ_Adapt time for lower line rates (e.g. 10.3125 Gbps).
(5) Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9 GHz between DS250DF230 and the measurement instrument.
(6) Measured with input data from DS280DF810 evaluation board, at 24.33024 Gbps or 10.1376 Gbps or 25.78125Gbps or 10.3125 Gbps.