SNLS396D January   2012  – January 2016 DS100MB203

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics - Serial Management Bus Interface
    7. 6.7 Timing Requirements - Serial Bus Interface
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 4-Level Input Configuration Guidelines
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Control Mode
      2. 7.4.2 SMBUS Mode
    5. 7.5 Programming
      1. 7.5.1 SMBUS Master Mode
    6. 7.6 Register Maps
      1. 7.6.1 System Management Bus (SMBus) and Configuration Registers
        1. 7.6.1.1 Transfer of Data Through the SMBus
        2. 7.6.1.2 SMBus Transactions
        3. 7.6.1.3 Writing a Register
        4. 7.6.1.4 Reading a Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Recommendations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

NJY Package
54-Pin WQFN
Top View (looking down through package)
DS100MB203 DS100MB203pinout.gif

Pin Functions: Common Connections(1)

PIN TYPE DESCRIPTION
NAME NO.
DIFFERENTIAL HIGH-SPEED INPUTS AND OUTPUTS
D_IN0+, D_IN0-,
D_IN1+, D_IN1-		 10, 11, 15, 16 I Inverting and noninverting CML differential inputs to the equalizer. A gated on-chip 50-Ω termination resistor connects D_INn+ to VDD and D_INn- to VDD when enabled. AC coupling required on high-speed I/O.
D_OUT0+, D_ OUT0-,
D_OUT1+, D_OUT1-		 3, 4, 7, 8 O Inverting and noninverting low power differential signaling 50-Ω outputs with de-emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O.
S_INA0+, S_INA0-,
S_INA1+, S_INA1-		 45, 44, 40, 39 I Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω termination resistor connects S_INAn+ to VDD and S_INAn- to VDD. AC coupling required on high-speed I/O.
S_INB0+, S_INB0-,
S_INB1+, S_INB1-		 43, 42, 38, 37 I Inverting and noninverting CML differential inputs to the equalizer. An on-chip 50-Ω termination resistor connects S_INBn+ to VDD and S_INBn- to VDD. AC coupling required on high-speed I/O.
S_OUTA0+, S_OUTA0-,
S_OUTA1+, S_OUTA1-		 35, 34, 31, 30 O Inverting and noninverting low power differential signaling 50-Ω outputs with de-emphasis. Fully compatible with AC-coupled CML inputs.
S_OUTB0+, S_OUTB0-,
S_OUTB1+, S_OUTB1-		 33, 32, 29, 28 O Inverting and noninverting low power differential signaling 50-Ω outputs with de-emphasis. Fully compatible with AC-coupled CML inputs. AC coupling required on high-speed I/O.
CONTROL PINS - SHARED (LVCMOS)
ENSMB 48 I, FLOAT,
LVCMOS		 System Management Bus (SMBus) enable pin
Tie 1 kΩ to VDD = register access SMBus slave mode
FLOAT = read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = Pin Mode
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
RESET 52 I, LVCMOS 0: Normal operation (device is enabled).
1: low power mode.
VDD_SEL 25 I, FLOAT Controls the internal regulator
FLOAT: 2.5-V mode
Tied to GND: 3.3-V mode
POWER
GND DAP Power Ground pad (DAP - die attach pad).
VDD 9, 14,36, 41, 51 Power Power supply pins CML/analog
2.5-V mode, connect to 2.5 V ±5%
3.3-V mode, connect 0.1-uF cap to each VDD pin
VIN 24 Power In 3.3-V mode, feed 3.3 V ±10% to VIN
In 2.5-V mode, leave floating.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3-V mode operation, VIN pin = 3.3 V and the "VDD" for the 4-level input is 3.3 V.
For 2.5-V mode operation, VDD pin = 2.5 V and the "VDD" for the 4-level input is 2.5 V.

Pin Functions: SMBus/EEPROM Control

PIN TYPE DESCRIPTION
NAME NO.
ENSMB = 1 (SMBUS SLAVE MODE), FLOAT (SMBUS MASTER MODE)
AD0-AD3 54, 53, 47, 46 I, LVCMOS ENSMB master or slave mode
SMBus slave address Inputs. In SMBus mode, these pins are the user set SMBus slave address inputs.
READ_EN 26 I, LVCMOS ENSMB = FLOAT (SMBUS master mode)
When using an external EEPROM, a transition from high to low starts the load from the external EEPROM
SCL 50 I, LVCMOS,
O, Open-drain		 ENSMB master or slave mode
SMBUS clock input pin is enabled (slave mode)
SMBUS clock output when loading configuration from EEPROM (master mode)
SDA 49 I, LVCMOS,
O, Open-drain		 ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pulldown only) output.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN 22 I, 4-LEVEL,
LVCMOS 		0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable, FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled with 50 Ω.
MODE 21 I, 4-LEVEL,
LVCMOS		 0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
SEL0 23 I, 4-LEVEL,
LVCMOS		 Select pin for Lane 0.
0: selects input S_INB0±, output S_OUTB0±.

20 kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
SEL1 26 I, 4-LEVEL,
LVCMOS		 Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.

20 kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.
OUTPUT (LVCMOS)
ALL_DONE 27 0, LVCMOS Valid Register Load Status Output
0: External EEPROM load passed
1: External EEPROM load failed

Pin Functions: Pin Control

PIN TYPE DESCRIPTION
NAME NO.
ENSMB = 0 (PIN MODE)
DEM_S0, DEM_S1
DEM_D0, DEM_D1		 49, 50, 53, 54 I, 4-LEVEL,
LVCMOS		 DEM_D[1:0] and DEM_S[1:0] control the level of VOD and de-emphasis on the high-speed output. The outputs are organized into two sides. The D side is controlled with the DEM_D[1:0] pins and the S side is controlled with the DEM_S[1:0] pins. See Table 3.
EQ_D0, EQ_D1
EQ_S0, EQ_S1		 20, 19, 46, 47 I, 4-LEVEL,
LVCMOS 		EQ_D[1:0] and EQ_S[1:0] control the level of equalization on the high-speed input pins. The inputs are organized into two sides. The D side is controlled with the EQ_D[1:0] pins and the S side is controlled with the EQ_S[1:0] pins. See Table 2.
CONTROL PINS—BOTH PIN AND SMBus MODES (LVCMOS)
INPUT_EN 22 I, 4-LEVEL,
LVCMOS 		0: Normal operation, FANOUT is disabled, use SEL0/1 to select the A or B input/output (see SEL0/1 pin), input always enabled with 50 Ω.
20kΩ to GND: Reserved
FLOAT: AUTO - Use RX Detect, SEL0/1 to determine which input or output to enable, FANOUT is disable
1: Normal operation, FANOUT is enabled (both S_OUT0/1 are ON). Input always enabled with 50 Ω.
MODE 21 I, 4-LEVEL,
LVCMOS		 0: SATA/SAS, PCIe GEN 1/2 and 10GE
FLOAT: AUTO (PCIe GEN 1/2 or GEN 3)
1: 10-KR
SEL0 23 I, 4-LEVEL,
LVCMOS		 Select pin for lane 0.
0: selects input S_INB0±, output S_OUTB0±.

20kΩ to GND: selects input S_INB0±, output S_OUTA0±.
FLOAT: selects input S_INA0±, output S_OUTB0±.
1: selects input S_INA0±, output S_OUTA0±.
SEL1 26 I, 4-LEVEL,
LVCMOS		 Select pin for Lane 1.
0: selects input S_INB1±, output S_OUTB1±.

20kΩ to GND: selects input S_INB1±, output S_OUTA1±.
FLOAT: selects input S_INA1±, output S_OUTB1±.
1: selects input S_INA1±, output S_OUTA1±.