ZHCSCX5A October 2014 – November 2015 DRV8848
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
- PWP|16
散热焊盘机械数据 (封装 | 引脚)
- PWP|16
订购信息
7 Detailed Description
7.1 Overview
The DRV8848 is an integrated motor driver solution for two DC motors or a bipolar stepper motor. The device integrates two H-bridges that use NMOS low-side drivers and PMOS high-side drivers and current sense regulation circuitry. The DRV8848 can be powered with a supply range between 4 to 18 V and is capable of providing an output current to 1-A rms.
A simple PWM interface allows easy interfacing to the controller circuit.
The current regulation uses a fixed off-time (tOFF) PWM scheme. The current regulation trip point is controlled by the value of the sense resistor and the voltage applied to VREF.
A low-power sleep mode is included, which allows the system to save power when not driving the motor.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 PWM Motor Drivers
DRV8848 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 6 shows a block diagram of the circuitry.
7.3.2 Bridge Control
Table 1 shows the logic for the inputs xIN1 and xIN2.
Table 1. Bridge Control
| xIN1 | xIN2 | xOUT1 | xOUT2 | Function (DC Motor) |
|---|---|---|---|---|
| 0 | 0 | Z | Z | Coast (fast decay) |
| 0 | 1 | L | H | Reverse |
| 1 | 0 | H | L | Forward |
| 1 | 1 | L | L | Brake (slow decay) |
SPACE
NOTE
Pins AIN1 and AIN2 are tri-level, so when they are left Hi-Z, they are not internally pulled to logic low. When AIN1 or AIN2 are set to Hi-Z and not in parallel mode, the output driver maintains the previous state.
7.3.3 Parallel Operation
The two drivers can be used in parallel to deliver twice the current to a single motor. To enter parallel mode, AIN1 and AIN2 must be left Hi-Z during power-up or when exiting sleep mode (nSLEEP toggling from 0 to 1). BIN1 and BIN2 are used to control the drivers. Tie AISEN and BISEN to a single sense resistor if current control is desired. To exit parallel mode, AIN1 and AIN2 must be driven high or low and the device must be powered-up or exit sleep mode. Figure 7 shows a block diagram of the device using parallel mode.
Figure 7. Parallel Mode Operation
7.3.4 Current Regulation
The current through the motor windings is regulated by a fixed-off-time PWM current regulation circuit. With DC brushed motors, current regulation can be used to limit the stall current (which is also the startup current) of the motor.
Current regulation works as follows:
When an H-bridge is enabled, current rises through the winding at a rate dependent on the supply voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current for a time tOFF before starting the next PWM cycle. Note that immediately after the current is enabled, the voltage on the xISEN pin is ignored for a period of time (tBLANK) before enabling the current sense circuitry. This blanking time also sets the minimum on-time of the PWM cycle.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor, connected to the xISEN pin, with a reference voltage. The reference voltage is derived from the voltage applied to the VREF pin and it is VVREF / 6.6. The VREF pin can be tied, on board, to the 3.3 V – VINT pin, or it can be externally forced to a desired VREF voltage.
The full scale chopping current in a winding is calculated as follows:
where
- IFS is the regulated current.
- VVREF is the voltage on the VREF pin.
- RISENSE is the resistance of the sense resistor.
Example: If VVREF is 3.3 V and a 500-mΩ sense resistor is used, the full-scale chopping current is 3.3 V / (6.6 × 500 mΩ) = 1 A.
Note that if the current control is not needed, the xISEN pins may be connected directly to ground. In this case, VREF should be connected to VINT.
7.3.5 Current Recirculation and Decay Modes
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached (see case 1 in Figure 8).
After the chopping current threshold is reached, the drive current is interrupted, but due to the inductive nature of the motor, current must continue to flow for some period of time. This is called recirculation current. To handle this recirculation current, the DRV8848 H-bridge operates in mixed decay mode.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the opposite drivers are turned on to allow the current to decay (see case 2 in Figure 8). If the winding current approaches zero, while in fast decay, the bridge is disabled to prevent any reverse current flow. In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge (see case 3 in Figure 8). Mixed decay starts with fast decay, then goes to slow decay. In DRV8848, the mixed decay ratio is 25% fast decay and 75% slow decay (as shown in Figure 9).
Figure 8. Decay Modes
Figure 9. Mixed Decay
7.3.6 Protection Circuits
The DRV8848 is fully protected against undervoltage, overcurrent, and overtemperature events.
7.3.6.1 OCP
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time tOCP, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The device remains disabled until the retry time tRETRY occurs. The OCP is independent for each H-bridge.
Overcurrent conditions are detected independently on both high-side and low-side devices; that is, a short to ground, supply, or across the motor winding all result in an OCP event. Note that OCP does not use the current sense circuitry used for PWM current control, so OCP functions even without presence of the xISEN resistors.
7.3.6.2 TSD
If the die temperature exceeds safe limits TTSD, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. After the die temperature has fallen to a safe level, operation automatically resumes. The nFAULT pin is released after operation has resumed.
7.3.6.3 UVLO
If at any time the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, and all internal logic is reset. Operation resumes when VVM rises above the UVLO rising threshold. The nFAULT pin is driven low during an undervoltage condition and is released after operation has resumed.
Table 2. Fault Handling
| FAULT | ERROR REPORT | H-BRIDGE | INTERNAL CIRCUITS | RECOVERY |
|---|---|---|---|---|
| VM undervoltage (UVLO) | nFAULT unlatched | Disabled | Shut down | System and fault clears on recovery |
| Overcurrent (OCP) | nFAULT unlatched | Disabled | Operating | System and fault clears on recovery and motor is driven after time, tRETRY |
| Thermal shutdown (TSD) | nFAULT unlatched | Disabled | Operating | System and fault clears on recovery |
7.4 Device Functional Modes
The DRV8848 is active unless the nSLEEP pin is brought logic low. In sleep mode, the VINT regulator is disabled and the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8848 is brought out of sleep mode automatically if nSLEEP is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.
When VVM falls below the VM UVLO threshold (VUVLO), the output driver, internal logic, and VINT regulator are reset.
Table 3. Functional Modes
| MODE | CONDITION | H-BRIDGE | VINT |
|---|---|---|---|
| Operating | 4 V < VVM < 18 V nSLEEP pin = 1 |
Operating | Operating |
| Sleep | 4 V < VVM < 18 V nSLEEP pin = 0 |
Disabled | Disabled |
| Fault | Any fault condition met | Disabled | Depends on fault |